Xiaoling Yi

According to our database, Xiaoling Yi authored at least 10 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning.

Stef Cuyckens, Xiaoling Yi, Nitish Satya Murthy, Chao Fang, Marian Verhelst

CoRR, May, 2025

DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators.

Xiaoling Yi, Yunhao Deng, Ryan Antonio, Fanchen Kong, Guilherme Paim, Marian Verhelst

CoRR, April, 2025

Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning.

Zheng Wu, Jinyi Shen, Xiaoling Yi, Li Shang, Fan Yang, Xuan Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.

Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Pereira Paim, Marian Verhelst

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.

Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Paim, Marian Verhelst

CoRR, 2024

SenseDSE: Sensitivity-Based Performance Evaluation for Design Space Exploration of Microarchitecture.

Zheng Wu, Xiaoling Yi, Li Shang, Fan Yang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

TPNoC: An Efficient Topology Reconfigurable NoC Generator.

Jiangnan Yu, Fan Yang, Xiaoling Yi, Chixiao Chen, Jun Tao, Dong Xu, Xiankui Xiong, Haitao Yang

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Graph Representation Learning for Microarchitecture Design Space Exploration.

Xiaoling Yi, Jialin Lu, Xiankui Xiong, Dong Xu, Li Shang, Fan Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.

Xiaoling Yi, Jiangnan Yu, Zheng Wu, Xiankui Xiong, Dong Xu, Chixiao Chen, Jun Tao, Fan Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Automated Compiler for RISC-V Based DNN Accelerator.

Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao, Fan Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022