Hai Helen Li
Orcid: 0000-0003-3228-6544Affiliations:
- Duke University, Department of Electrical and Computer Engineering
- University of Pittsburgh, Department of Electrical and Computer Engineering
- NYU Polytechnic Institute, Department of Electrical and Computer Engineering
- Seagate Technology LLC, Bloomington, USA
- Intel Corporation, Santa Clara, USA
- Qualcomm Inc., San Diego, USA
- Purdue University, Electrical and Computer Engineering
According to our database1,
Hai Helen Li
authored at least 412 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2021, "For contributions to neuromorphic computing and deep-learning acceleration".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on scopus.com
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on linkedin.com
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on orcid.org
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on ei-lab.org
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on ece.duke.edu
On csauthors.net:
Bibliography
2024
IEEE Trans. Computers, May, 2024
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
CoRR, 2024
Efficient, Direct, and Restricted Black-Box Graph Evasion Attacks to Any-Layer Graph Neural Networks via Influence Function.
Proceedings of the 17th ACM International Conference on Web Search and Data Mining, 2024
2023
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2023.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference.
ACM Trans. Embed. Comput. Syst., October, 2023
ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
IEEE Trans. Computers, March, 2023
IEEE Des. Test, February, 2023
MWSCAS Guest Editorial Special Issue Based on the 64th International Midwest Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
IEEE Trans. Emerg. Top. Comput., 2023
In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search.
CoRR, 2023
SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models.
CoRR, 2023
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators.
CoRR, 2023
CoRR, 2023
HCE: Improving Performance and Efficiency with Heterogeneously Compressed Neural Network Ensemble.
CoRR, 2023
Proceedings of the ACM Web Conference 2023, 2023
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Mixture Outlier Exposure: Towards Out-of-Distribution Detection in Fine-grained Environments.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers.
Proceedings of the International Conference for High Performance Computing, 2023
Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AI.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the International Joint Conference on Neural Networks, 2023
Fed-CBS: A Heterogeneity-Aware Client Sampling Mechanism for Federated Learning via Class-Imbalance Reduction.
Proceedings of the International Conference on Machine Learning, 2023
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Stable and Causal Inference for Discriminative Self-supervised Deep Visual Representations.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
INCA: Input-stationary Dataflow at Outside-the-box Thinking about Deep Learning Accelerators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the ECAI 2023 - 26th European Conference on Artificial Intelligence, September 30 - October 4, 2023, Kraków, Poland, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Proceedings of the Conference on Lifelong Learning Agents, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
ACM Trans. Embed. Comput. Syst., November, 2022
ACM Trans. Embed. Comput. Syst., September, 2022
Toward Efficient and Adaptive Design of Video Detection System with Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2022
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2022.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Des. Test, 2022
More Generalized and Personalized Unsupervised Representation Learning In A Distributed System.
CoRR, 2022
FADE: Enabling Large-Scale Federated Adversarial Training on Resource-Constrained Edge Devices.
CoRR, 2022
Learning and Compositionality: a Unification Attempt via Connectionist Probabilistic Programming.
CoRR, 2022
Enabling AI Innovation via Data and Model Sharing: An Overview of the Nsf Convergence Accelerator Track D.
AI Mag., 2022
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022
FedSEA: A Semi-Asynchronous Federated Learning Framework for Extremely Heterogeneous Devices.
Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems, 2022
A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
GraphFL: A Federated Learning Framework for Semi-Supervised Node Classification on Graphs.
Proceedings of the IEEE International Conference on Data Mining, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the Computer Vision - ECCV 2022, 2022
RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022
FedCor: Correlation-Based Active Client Selection Strategy for Heterogeneous Federated Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
Proceedings of the 8th IEEE International Conference on Collaboration and Internet Computing, 2022
Proceedings of the International Conference on Automated Machine Learning, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
2021
ACM Trans. Embed. Comput. Syst., 2021
ACM Trans. Cyber Phys. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Dynamic Regularization on Activation Sparsity for Neural Network Efficiency Improvement.
ACM J. Emerg. Technol. Comput. Syst., 2021
Efficient neural network using pointwise convolution kernels with linear phase constraint.
Neurocomputing, 2021
CoRR, 2021
FedMask: Joint Computation and Communication-Efficient Personalized Federated Learning via Heterogeneous Masking.
Proceedings of the SenSys '21: The 19th ACM Conference on Embedded Networked Sensor Systems, Coimbra, Portugal, November 15, 2021
FL-WBC: Enhancing Robustness against Model Poisoning Attacks in Federated Learning from a Client Perspective.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the ACM MobiCom '21: The 27th Annual International Conference on Mobile Computing and Networking, 2021
ESCALATE: Boosting the Efficiency of Sparse CNN Accelerator with Kernel Decomposition.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the KDD '21: The 27th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2021
Privacy-Preserving Representation Learning on Graphs: A Mutual Information Perspective.
Proceedings of the KDD '21: The 27th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2021
1S1R-Based Stable Learning through Single-Spike-Encoded Spike-Timing-Dependent Plasticity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Defending against GAN-based DeepFake Attacks via Transformation-aware Adversarial Faces.
Proceedings of the International Joint Conference on Neural Networks, 2021
LotteryFL: Empower Edge Intelligence with Personalized and Communication-Efficient Federated Learning.
Proceedings of the 6th IEEE/ACM Symposium on Edge Computing, 2021
Proceedings of the 38th International Conference on Machine Learning, 2021
Proceedings of the 9th International Conference on Learning Representations, 2021
Can Targeted Adversarial Examples Transfer When the Source and Target Models Have No Label Space Overlap?
Proceedings of the IEEE/CVF International Conference on Computer Vision Workshops, 2021
Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Rerec: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Reinforcement Learning-based Black-Box Evasion Attacks to Link Prediction in Dynamic Graphs.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Soteria: Provable Defense Against Privacy Leakage in Federated Learning From Representation Perspective.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021
Proceedings of the Third IEEE International Conference on Cognitive Machine Intelligence, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Efficient FPGA Implementation of a Convolutional Neural Network for Radar Signal Processing.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2.
ACM J. Emerg. Technol. Comput. Syst., 2020
Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.
ACM J. Emerg. Technol. Comput. Syst., 2020
3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2020
A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications.
Int. J. Semantic Comput., 2020
Neurocomputing, 2020
Introduction to the Special Issue on the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Provable Defense against Privacy Leakage in Federated Learning from Representation Perspective.
CoRR, 2020
GraphFL: A Federated Learning Framework for Semi-Supervised Node Classification on Graphs.
CoRR, 2020
CoRR, 2020
Reinforcement Learning-based Black-Box Evasion Attacks to Link Prediction in Dynamic Graphs.
CoRR, 2020
LotteryFL: Personalized and Communication-Efficient Federated Learning with Lottery Ticket Hypothesis on Non-IID Datasets.
CoRR, 2020
IEEE Consumer Electron. Mag., 2020
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020
Leveraging 3D Vertical RRAM to Developing Neuromorphic Architecture for Pattern Classification.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Redistributing and Re-Stylizing Features for Training a Fast Photorealistic Stylizer.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Conditional Transferring Features: Scaling GANs to Thousands of Classes with 30% Less High-Quality Data for Training.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 37th International Conference on Machine Learning, 2020
DeepHoyer: Learning Sparser Neural Network with Differentiable Scale-Invariant Sparsity Measures.
Proceedings of the 8th International Conference on Learning Representations, 2020
MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the Computer Vision - ECCV 2020, 2020
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Learning Low-rank Deep Neural Networks via Singular Vector Orthogonality Regularization and Singular Value Sparsification.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
Proceedings of the 19th International Conference on Autonomous Agents and Multiagent Systems, 2020
Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses.
IEEE Trans. Computers, 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152).
Dagstuhl Reports, 2019
Conditional Transferring Features: Scaling GANs to Thousands of Classes with 30% Less High-quality Data for Training.
CoRR, 2019
Towards Efficient and Secure Delivery of Data for Deep Learning with Privacy-Preserving.
CoRR, 2019
SwiftNet: Using Graph Propagation as Meta-knowledge to Search Highly Representative Neural Architectures.
CoRR, 2019
ReBNN: in-situ acceleration of binarized neural networks in ReRAM using complementary resistive cell.
CCF Trans. High Perform. Comput., 2019
Resistive Memory-Based In-Memory Computing: From Device and Large-Scale Integration System Perspectives.
Adv. Intell. Syst., 2019
Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019
Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 31st IEEE International Conference on Tools with Artificial Intelligence, 2019
Joint Regularization on Activations and Weights for Efficient Neural Network Pruning.
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019
Taming extreme heterogeneity via machine learning based design of autonomous manycore systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Proceedings of the Cloud Computing - CLOUD 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
Bamboo: Ball-Shape Data Augmentation Against Adversarial Attacks from All Directions.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
Guest Editorial: Special Issue on Large-Scale Memristive Systems and Neurochips for Computational Intelligence.
IEEE Trans. Emerg. Top. Comput. Intell., 2018
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
J. Circuits Syst. Comput., 2018
Integr., 2018
Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Towards Leveraging the Information of Gradients in Optimization-based Adversarial Attack.
CoRR, 2018
CoRR, 2018
LEASGD: an Efficient and Privacy-Preserving Decentralized Algorithm for Distributed Learning.
CoRR, 2018
CoRR, 2018
SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning.
CoRR, 2018
Sci. China Inf. Sci., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 6th International Conference on Learning Representations, 2018
SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Real-Time Cardiac Arrhythmia Classification Using Memristor Neuromorphic Computing System.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Computers, 2017
CoRR, 2017
CoRR, 2017
Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.
IEEE Consumer Electron. Mag., 2017
IEEE Access, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017
Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Hardware implementation of echo state networks using memristor double crossbar arrays.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 5th International Conference on Learning Representations, 2017
Proceedings of the IEEE International Conference on Computer Vision, 2017
A closed-loop design to enhance weight stability of memristor based neural network chips.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
A Compact DNN: Approaching GoogLeNet-Level Accuracy of Classification and Domain Adaptation.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017
Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
J. Signal Process. Syst., 2016
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration.
ACM Trans. Design Autom. Electr. Syst., 2016
IEEE Trans. Multi Scale Comput. Syst., 2016
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.
Neural Comput. Appl., 2016
IET Cyper-Phys. Syst.: Theory & Appl., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016
Proceedings of the Advances in Neural Information Processing Systems 29: Annual Conference on Neural Information Processing Systems 2016, 2016
Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Security challenges in smart surveillance systems and the solutions based on emerging nano-devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
The evolutionary spintronic technologies and their usage in high performance computing.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Cloning your mind: security challenges in cognitive system designs and their solutions.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Neural Networks Learn. Syst., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Bio-inspired computing with resistive memories - models, architectures and applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Accelerating graph computation with racetrack memory and pointer-assisted graph representation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.
ACM Trans. Design Autom. Electr. Syst., 2013
ACM Trans. Archit. Code Optim., 2013
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.
ACM J. Emerg. Technol. Comput. Syst., 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Cross-layer racetrack memory design for ultra high density and low power consumption.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2013
2012
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
IEEE J. Solid State Circuits, 2012
ACM J. Emerg. Technol. Comput. Syst., 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Memristor-based synapse design and training scheme for neuromorphic computing architecture.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
J. Low Power Electron., 2011
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Comput. Digit. Tech., 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2009
ACM Trans. Archit. Code Optim., 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.
Proceedings of the 27th International Conference on Computer Design, 2009
An overview of non-volatile memory technology and the implication for tools and architectures.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008
2007
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
2006
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Cascaded carry-select adder (C<sup>2</sup>SA): a new structure for low-power CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
2003
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003