Hai Helen Li

According to our database1, Hai Helen Li authored at least 246 papers between 2003 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses.
IEEE Trans. Computers, 2019

Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152).
Dagstuhl Reports, 2019

Towards Efficient and Secure Delivery of Data for Deep Learning with Privacy-Preserving.
CoRR, 2019

RED: A ReRAM-based Deconvolution Accelerator.
CoRR, 2019

SwiftNet: Using Graph Propagation as Meta-knowledge to Search Highly Representative Neural Architectures.
CoRR, 2019

Thread Batching for High-performance Energy-efficient GPU Memory Design.
CoRR, 2019

AutoGrow: Automatic Layer Growing in Deep Convolutional Networks.
CoRR, 2019

Snooping Attacks on Deep Reinforcement Learning.
CoRR, 2019

HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array.
CoRR, 2019

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Learning Efficient Sparse Structures in Speech Recognition.
Proceedings of the IEEE International Conference on Acoustics, 2019

HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

RED: A ReRAM-based Deconvolution Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards Decentralized Deep Learning with Differential Privacy.
Proceedings of the Cloud Computing - CLOUD 2019, 2019

NeuralHMC: an efficient HMC-based accelerator for deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Build reliable and efficient neuromorphic design with memristor technology.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Exploration of Automatic Mixed-Precision Search for Deep Neural Networks.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Bamboo: Ball-Shape Data Augmentation Against Adversarial Attacks from All Directions.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

DPATCH: An Adversarial Patch Attack on Object Detectors.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

2018
Guest Editorial: Special Issue on Large-Scale Memristive Systems and Neurochips for Computational Intelligence.
IEEE Trans. Emerging Topics in Comput. Intellig., 2018

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.
Journal of Circuits, Systems, and Computers, 2018

Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view.
Integration, 2018

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Towards Leveraging the Information of Gradients in Optimization-based Adversarial Attack.
CoRR, 2018

Adversarial Attacks for Optical Flow-Based Action Recognition Classifiers.
CoRR, 2018

LEASGD: an Efficient and Privacy-Preserving Decentralized Algorithm for Distributed Learning.
CoRR, 2018

Differentiable Fine-grained Quantization for Deep Neural Network Compression.
CoRR, 2018

DPatch: Attacking Object Detectors with Adversarial Patches.
CoRR, 2018

SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning.
CoRR, 2018

Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation.
CoRR, 2018

Challenges of memristor based neuromorphic computing system.
SCIENCE CHINA Information Sciences, 2018

MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design and Data Management for Magnetic Racetrack Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Learning Intrinsic Sparse Structures within Long Short-Term Memory.
Proceedings of the 6th International Conference on Learning Representations, 2018

SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting.
Proceedings of the International Conference on Computer-Aided Design, 2018

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

GraphR: Accelerating Graph Processing Using ReRAM.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Real-Time Cardiac Arrhythmia Classification Using Memristor Neuromorphic Computing System.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReRAM-based accelerator for deep learning.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReCom: An efficient resistive accelerator for compressed deep neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A neuromorphic design using chaotic mott memristor with relaxation oscillation.
Proceedings of the 55th Annual Design Automation Conference, 2018

Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Running sparse and low-precision neural network: When algorithm meets hardware.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Spintronics based stochastic computing for efficient Bayesian inference system.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Process variation aware data management for magnetic skyrmions racetrack memory.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Editorial.
IEEE Trans. VLSI Syst., 2017

Cross-Layer Optimization for Multilevel Cell STT-RAM Caches.
IEEE Trans. VLSI Syst., 2017

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.
IEEE Trans. Computers, 2017

Giant Spin-Hall assisted STT-RAM and logic design.
Integration, 2017

Recent Technology Advances of Emerging Memories.
IEEE Design & Test, 2017

Spintronics based Stochastic Computing for Efficient Bayesian Inference System.
CoRR, 2017

Learning Intrinsic Sparse Structures within Long Short-term Memory.
CoRR, 2017

GraphR: Accelerating Graph Processing Using ReRAM.
CoRR, 2017

Generative Poisoning Attack Method Against Neural Networks.
CoRR, 2017

A Compact DNN: Approaching GoogLeNet-Level Accuracy of Classification and Domain Adaptation.
CoRR, 2017

TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning.
CoRR, 2017

Coordinating Filters for Faster Deep Neural Networks.
CoRR, 2017

Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses.
CoRR, 2017

Group Scissor: Scaling Neuromorphic Computing Design to Big Neural Networks.
CoRR, 2017

A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks.
CoRR, 2017

Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.
IEEE Consumer Electronics Magazine, 2017

Power Allocation for Cache-Aided Small-Cell Networks With Limited Backhaul.
IEEE Access, 2017

W1A: Memories.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning.
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017

Brain-inspired computing accelerated by memristor technology.
Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017

The New Large-Scale RNNLM System Based on Distributed Neuron.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Hardware implementation of echo state networks using memristor double crossbar arrays.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Faster CNNs with Direct Sparse Convolutions and Guided Pruning.
Proceedings of the 5th International Conference on Learning Representations, 2017

Coordinating Filters for Faster Deep Neural Networks.
Proceedings of the IEEE International Conference on Computer Vision, 2017

A closed-loop design to enhance weight stability of memristor based neural network chips.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AdaLearner: An adaptive distributed mobile learning system for neural networks.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

An FPGA Design Framework for CNN Sparsification and Acceleration.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Rescuing Memristor-based Neuromorphic Design with High Defects.
Proceedings of the 54th Annual Design Automation Conference, 2017

A Compact DNN: Approaching GoogLeNet-Level Accuracy of Classification and Domain Adaptation.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017

Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Neuromorphic Architecture for Context Aware Text Image Recognition.
Signal Processing Systems, 2016

Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration.
ACM Trans. Design Autom. Electr. Syst., 2016

Guest Editorial: Design and Applications of Neuromorphic Computing System.
IEEE Trans. Multi-Scale Computing Systems, 2016

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. on Circuits and Systems, 2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Array Organization and Data Management Exploration in Racetrack Memory.
IEEE Trans. Computers, 2016

Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.
Neural Computing and Applications, 2016

ApesNet: a pixel-wise efficient segmentation network for embedded devices.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Spintronic Memristor as Interface Between DNA and Solid State Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A New Learning Method for Inference Accuracy, Core Occupation, and Performance Co-optimization on TrueNorth Chip.
CoRR, 2016

Learning Structured Sparsity in Deep Neural Networks.
CoRR, 2016

Holistic SparseCNN: Forging the Trident of Accuracy, Speed, and Size.
CoRR, 2016

Spin-Hall Assisted STT-RAM Design and Discussion.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

Objnandsim: object-based NAND flash device simulator.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Learning Structured Sparsity in Deep Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 29: Annual Conference on Neural Information Processing Systems 2016, 2016

Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A neuromorphic ASIC design using one-selector-one-memristor crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Security of neuromorphic systems: Challenges and solutions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Heterogeneous systems with reconfigurable neuromorphic computing accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Built-in selectors self-assembled into memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Neural processor design enabled by memristor technology.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Design techniques of eNVM-enabled neuromorphic computing systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Security challenges in smart surveillance systems and the solutions based on emerging nano-devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

The Applications of NVM Technology in Hardware Security.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

ApesNet: A Pixel-wise Efficient Segmentation Network.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip.
Proceedings of the 53rd Annual Design Automation Conference, 2016

TEMP: thread batch enabled memory partitioning for GPU.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A novel PUF based on cell error rate distribution of STT-RAM.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Read Performance: The Newest Barrier in Scaled STT-RAM.
IEEE Trans. VLSI Syst., 2015

An overview on memristor crossabr based neuromorphic circuit and architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

The evolutionary spintronic technologies and their usage in high performance computing.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Hardware acceleration for neuromorphic computing: An evolving view.
Proceedings of the 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 2015

A new self-reference sensing scheme for TLC MRAM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

The applications of memristor devices in next-generation cortical processor designs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Energy Efficient RRAM Spiking Neural Network for Real Time Classification.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Hierarchical library based power estimator for versatile FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

FPGA Acceleration of Recurrent Neural Network Based Language Model.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Giant spin hall effect (GSHE) logic design for low power application.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A spiking neuromorphic design with resistive crossbar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Cloning your mind: security challenges in cognitive system designs and their solutions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Vortex: variation-aware training for memristor X-bar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

FlexLevel: a novel NAND flash storage system design for LDPC latency reduction.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Spiking-based matrix computation by leveraging memristor crossbar array.
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An efficient STT-RAM-based register file in GPU architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
STT-RAM Cache Hierarchy With Multiretention MTJ Designs.
IEEE Trans. VLSI Syst., 2014

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study.
IEEE Trans. Neural Netw. Learning Syst., 2014

Emerging memristor technology enabled next generation cortical processor.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Neuromorphic acceleration for context aware text image recognition.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory Array.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Memristor Modeling - Static, Statistical, and Stochastic Methodologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Design exploration of racetrack lower-level caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper).
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Bio-inspired computing with resistive memories - models, architectures and applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An adjustable memristor model and its application in small-world neural networks.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

STDP learning rule based on memristor with STDP property.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A heterogeneous computing system with memristor-based neuromorphic accelerators.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

ICE: Inline calibration for memristor crossbar-based computing engine.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.
ACM Trans. Design Autom. Electr. Syst., 2013

C1C: A configurable, compiler-guided STT-RAM L1 cache.
TACO, 2013

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.
JETC, 2013

A pseudo-weighted sensing scheme for memristor based cross-point memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

A practical low-power memristor-based analog neural branch predictor.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Memristor-based synapse design and a case study in reconfigurable systems.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Unleashing the potential of MLC STT-RAM caches.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A hardware security scheme for RRAM-based FPGA.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems.
Proceedings of the Design, Automation and Test in Europe, 2013

STT-RAM designs supporting dual-port accesses.
Proceedings of the Design, Automation and Test in Europe, 2013

Cross-layer racetrack memory design for ultra high density and low power consumption.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

BSB training scheme implementation on memristor-based circuit.
Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2013

2012
Low-Power Design of Emerging Memory Technologies.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory.
IEEE Trans. VLSI Syst., 2012

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
J. Solid-State Circuits, 2012

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder.
JETC, 2012

Memristor in neuromorphic computing.
Proceedings of the IEEE 25th International SOC Conference, 2012

Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A dual-mode architecture for fast-switching STT-RAM.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Process variation aware data management for STT-RAM cache design.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A novel peripheral circuit for RRAM-based LUT.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Memristor-based synapse design and training scheme for neuromorphic computing architecture.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Memristor crossbar based hardware realization of BSB recall function.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Non-volatile 3D stacking RRAM-based FPGA.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Architecting a common-source-line array for bipolar non-volatile memory devices.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Spintronic memristor based temperature sensor design with CMOS current reference.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Statistical memristor modeling and case study in neuromorphic computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Hardware realization of BSB recall function using memristor crossbar arrays.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A Look Up Table design with 3D bipolar RRAMs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Fine-grained dynamic voltage scaling on OLED display.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Spintronic Memristor: Compact Model and Statistical Analysis.
J. Low Power Electronics, 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Computers & Digital Techniques, 2011

3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Multi retention level STT-RAM cache designs with a dynamic refresh scheme.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Processor caches with multi-level spin-transfer torque ram cells.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Universal statistical cure for predicting memory loss.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast statistical model of TiO2 thin-film memristor and design implication.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.
Proceedings of the Design, Automation and Test in Europe, 2011

Emerging non-volatile memories: opportunities and challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Geometry variations analysis of TiO2 thin-film and spintronic memristors.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Emerging sensing techniques for emerging memories.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies.
IEEE Trans. VLSI Syst., 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
IEEE Trans. VLSI Syst., 2010

Scalability of PCMO-based resistive switch device in DSM technologies.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Compact model of memristors and its application in computing systems.
Proceedings of the Design, Automation and Test in Europe, 2010

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. VLSI Syst., 2009

Tolerating process variations in large, set-associative caches: The buddy cache.
TACO, 2009

Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.
Proceedings of the 27th International Conference on Computer Design, 2009

An overview of non-volatile memory technology and the implication for tools and architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM).
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008

2007
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

VOSCH: Voltage scaled cache hierarchies.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. VLSI Syst., 2004

2003
Deterministic Clock Gating for Microprocessor Power Reduction.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003


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