Xun Jiang

According to our database, Xun Jiang authored at least 16 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement.

Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin

Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

DSR: A Systematic Approach for Efficient Double-sided Signal Routing.

Jianqing Chen, Zhenkun Lin, Xun Jiang, Genggeng Liu, Yibo Lin, Gang Du

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction.

Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2025

A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections.

Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

DeepLayout: Learning Neural Representations of Circuit Placement Layout.

Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Qiang Xu, Runsheng Wang, Yibo Lin

Proceedings of the Forty-second International Conference on Machine Learning, 2025

GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection.

Chunyuan Zhao, Jiarui Wang, Xun Jiang, Jincheng Lou, Yibo Lin

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals.

Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang

Proceedings of the Design, Automation & Test in Europe Conference, 2025

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.

Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects.

Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment.

Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the Twelfth International Conference on Learning Representations, 2024

Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation.

Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing.

Jiarui Wang, Xun Jiang, Yibo Lin

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning.

Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.

Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.

Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

FPGA-Accelerated Maze Routing Kernel for VLSI Designs.

Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022