Chen Zhang

Orcid: 0000-0003-2762-2726

Affiliations:
  • Shanghai Jiao Tong University, China
  • Alibaba DAMO Academy, Shanghai, China (former)
  • Microsoft Research Asia (former)
  • Peking University, Center for Energy-Efficient Computing and Applications (CECA), Beijing, China (former)


According to our database1, Chen Zhang authored at least 73 papers between 2013 and 2026.

Collaborative distances:

Timeline

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Bibliography

2026
HiRe: A Hierarchical Reconfigurable Architecture for Large-Scale Multichiplet DNN Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., June, 2026

MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems.
CoRR, May, 2026

Towards Compute-Aware In-Switch Computing for LLMs Tensor-Parallelism on Multi-GPU Systems.
CoRR, May, 2026

Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs.
CoRR, May, 2026

TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence.
CoRR, February, 2026

M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization.
CoRR, January, 2026

Towards Compute-Aware In-Switch Computing for LLMs Tensor-Parallelism on Multi-GPU Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

FlashFuser: Expanding the Scale of Kernel Fusion for Compute-Intensive Operators via Inter-Core Connection.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

M<sup>2</sup>XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2025

ClusterFusion: Expanding Operator Fusion Scope for LLM Inference via Cluster-Level Collective Primitive.
CoRR, August, 2025

Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2025

ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis.
CoRR, July, 2025

Accelerating 3D Gaussian Splatting with Neural Sorting and Axis-Oriented Rasterization.
CoRR, June, 2025

Scaling Laws for Speculative Decoding.
CoRR, May, 2025

DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization.
CoRR, March, 2025

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators.
CoRR, March, 2025

DSTC: Dual-Side Sparse Tensor Core for DNNs Acceleration on Modern GPU Architectures.
IEEE Trans. Computers, February, 2025

Data and System Perspectives of Sustainable Artificial Intelligence.
CoRR, January, 2025

DWCLF-Net: A weighted contrastive learning feature fusion network for temporal scar image sequence classification.
Biomed. Signal Process. Control., 2025

Jenga: Effective Memory Management for Serving LLM with Heterogeneity.
Proceedings of the ACM SIGOPS 31st Symposium on Operating Systems Principles, 2025

PrefillOnly: An Inference Engine for Prefill-only Workloads in Large Language Model Applications.
Proceedings of the ACM SIGOPS 31st Symposium on Operating Systems Principles, 2025

FlashTensor: Optimizing Tensor Programs by Leveraging Fine-grained Tensor Property.
Proceedings of the 30th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2025

H<sup>2</sup>-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

TB-STC: Transposable Block-wise N: M Structured Sparse Tensor Core.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT Computation.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

SynGPU: Synergizing CUDA and Bit-Serial Tensor Cores for Vision Transformer Acceleration on GPU.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

IntelliGen: Instruction-Level Auto-tuning for Tensor Program with Monotonic Memory Optimization.
Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025

2024
Graph-Centric Performance Analysis for Large-Scale Parallel Applications.
IEEE Trans. Parallel Distributed Syst., July, 2024

MAGPY: Compiling Eager Mode DNN Programs by Monitoring Execution States.
Proceedings of the 2024 USENIX Annual Technical Conference, 2024

MixQ: Taming Dynamic Outliers in Mixed-Precision Quantization by Online Prediction.
Proceedings of the International Conference for High Performance Computing, 2024

Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Amanda: Unified Instrumentation Framework for Deep Neural Networks.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
PowerFusion: A Tensor Compiler with Explicit Data Movement Description and Instruction-level Graph IR.
CoRR, 2023

Cocktailer: Analyzing and Optimizing Dynamic Control Flow in Deep Learning.
Proceedings of the 17th USENIX Symposium on Operating Systems Design and Implementation, 2023

Cambricon-R: A Fully Fused Accelerator for Real-Time Learning of Neural Scene Representation.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks.
Proceedings of the ACM Turing Award Celebration Conference - China 2023, 2023

2022
Critique of "MemXCT: Memory-Centric X-Ray CT Reconstruction With Massive Parallelization" by SCC Team From Tsinghua University.
IEEE Trans. Parallel Distributed Syst., 2022

UniQ: A Unified Programming Model for Efficient Quantum Circuit Simulation.
Proceedings of the SC22: International Conference for High Performance Computing, 2022

PerFlow: a domain specific framework for automatic performance analysis of parallel applications.
Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022

FreeTensor: a free-form DSL with holistic optimizations for irregular tensor programs.
Proceedings of the PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation, San Diego, CA, USA, June 13, 2022

ROLLER: Fast and Efficient Tensor Compilation for Deep Learning.
Proceedings of the 16th USENIX Symposium on Operating Systems Design and Implementation, 2022

ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Calibration of the Multiple Choice Machine Reading Comprehension.
Proceedings of the International Joint Conference on Neural Networks, 2022

Efficiently emulating high-bitwidth computation with low-bitwidth hardware.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

SQuant: On-the-Fly Data-Free Quantization via Diagonal Hessian Approximation.
Proceedings of the Tenth International Conference on Learning Representations, 2022

Nesting Forward Automatic Differentiation for Memory-Efficient Deep Neural Network Training.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Critique of "Planetary Normal Mode Computation: Parallel Algorithms, Performance, and Reproducibility" by SCC Team From Tsinghua University.
IEEE Trans. Parallel Distributed Syst., 2021

A Fast Lock for Explicit Message Passing Architectures.
IEEE Trans. Computers, 2021

Eden: A Unified Environment Framework for Booming Reinforcement Learning Algorithms.
CoRR, 2021

Boosting Mobile CNN Inference through Semantic Memory.
Proceedings of the MM '21: ACM Multimedia Conference, Virtual Event, China, October 20, 2021

Dual-side Sparse Tensor Core.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

HyQuas: hybrid partitioner based quantum circuit simulation system on GPU.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

2020
Deeper Insights into Weight Sharing in Neural Architecture Search.
CoRR, 2020

SCYLLA: QoE-aware Continuous Mobile Vision with FPGA-based Dynamic Deep Neural Network Reconfiguration.
Proceedings of the 39th IEEE Conference on Computer Communications, 2020

LadaBERT: Lightweight Adaptation of BERT through Hybrid Model Compression.
Proceedings of the 28th International Conference on Computational Linguistics, 2020

2019
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Live Video Analytics with FPGA-based Smart Cameras.
Proceedings of the 2019 Workshop on Hot Topics in Video Analytics and Intelligent Edges, 2019

Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

SeerNet: Predicting Convolutional Neural Network Feature-Map Sparsity Through Low-Bit Quantization.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Balanced Sparsity for Efficient DNN Inference on GPU.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018
Best-Effort FPGA Programming: A Few Steps Can Go a Long Way.
CoRR, 2018

2017
Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators.
Proceedings of the Advanced Parallel Processing Technologies, 2017

2016
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
An efficient design and implementation of LSM-tree based key-value store on open-channel SSD.
Proceedings of the Ninth Eurosys Conference 2014, 2014

2013
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Memory partitioning for multidimensional arrays in high-level synthesis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


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