Yasuo Inoue

According to our database, Yasuo Inoue authored at least 5 papers between 1991 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory.

Mitsuo Usami, Hisao Tanabe, Akira Sato, Isao Sakama, Yukio Maki, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

1998

Development of Automated Construction System for High-Rise Reinforced Concrete Buildings.

Koji Hamada, Noriyuki Furuya, Yasuo Inoue, Tatsuya Wakisaka

Proceedings of the IEEE International Conference on Robotics and Automation, 1998

1997

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique.

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

IEEE J. Solid State Circuits, 1997

1994

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology.

Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutarni Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

1991

A 21-mW 4-Mb CMOS SRAM for battery operation.

Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami

IEEE J. Solid State Circuits, November, 1991