Kazuyasu Fujishima

According to our database1, Kazuyasu Fujishima authored at least 9 papers between 1986 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2005
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.
IEEE J. Solid State Circuits, 2005

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.
IEEE J. Solid State Circuits, 2005

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.
IEICE Trans. Electron., 2005

2000
High-performance embedded SOI DRAM architecture for the low-power supply.
IEEE J. Solid State Circuits, 2000

1993
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.
IEEE Des. Test Comput., 1993

1992
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990
The cache DRAM architecture: a DRAM with an on-chip cache memory.
IEEE Micro, 1990

1989
A New Array Architecture for Parallel Testing in VLSI Memories.
Proceedings of the Proceedings International Test Conference 1989, 1989

1986
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
Proceedings of the Proceedings International Test Conference 1986, 1986


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