Yasuto Kuroda

According to our database, Yasuto Kuroda authored at least 19 papers between 2005 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching.

Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Yuji Yano, Shoji Koyama

Photonic Netw. Commun., 2016

Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure.

Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka

Proceedings of the 13th IEEE Annual Consumer Communications & Networking Conference, 2016

2015

Demonstrating 100 Gbps optical packet switching using 16-bit longest prefix matching forwarding engine.

Hideaki Furukawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama

Proceedings of the 2015 International Conference on Optical Network Design and Modeling, 2015

2014

Development of onboard LPM-based header processing and reactive link selection for optical packet and circuit integrated networks.

Hideaki Furukawa, Takaya Miyazawa, Hiroaki Harai, Yasuto Kuroda, Shoji Koyama, Shin'ichi Arakawa, Masayuki Murata

Proceedings of the IEEE International Conference on Communications, 2014

2013

A study on micro level traffic prediction for energy-aware routers.

Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka

ACM SIGOPS Oper. Syst. Rev., 2013

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.

Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai

IEEE J. Solid State Circuits, 2013

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka

IEICE Trans. Electron., 2013

Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue

IEICE Trans. Commun., 2013

2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving.

Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka

Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013

2012

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine.

Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka

IEICE Trans. Commun., 2012

A slice structure using the management of network traffic prediction for green IT.

Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue

Proceedings of the 13th IEEE International Conference on High Performance Switching and Routing, 2012

A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application.

Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Deterministic High Density Packet-Buffer System for Low Cost Network Systems.

Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue

Proceedings of the IEEE 26th International Conference on Advanced Information Networking and Applications, 2012

2010

Hardware implementation of fast forwarding engine using standard memory and dedicated circuit.

Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2008

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.

Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

IEICE Trans. Electron., 2008

2007

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.

Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

IEICE Trans. Inf. Syst., 2007

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.

Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

IEICE Trans. Inf. Syst., 2007

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.

Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].

Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005