Yaswanth K. Cherivirala

According to our database, Yaswanth K. Cherivirala authored at least 4 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm.

Yaswanth K. Cherivirala, David D. Wentzloff

IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation.

Yaswanth K. Cherivirala, Mehdi Saligane, David D. Wentzloff

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2020

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.

Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff

Proceedings of the VLSI-SoC: Design Trends, 2020

An Open-source Framework for Autonomous SoC Design with Analog Block Generation.

Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020