Morteza Fayazi

According to our database, Morteza Fayazi authored at least 20 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Non-Intrusive THz Chiplet Calibration Using Deep Neural Networks.

Amirata Tabatabavakili, Mohammed Ayman Habib, Osei Brempong, Morteza Fayazi, Ehsan Afshari

Proceedings of the 44th IEEE VLSI Test Symposium, 2026

SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence.

Saoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Soroosh Noorzad, Morteza Fayazi

Proceedings of the Design, Automation & Test in Europe Conference, 2026

MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation.

Pravallika Abbineni, Saoud Aldowaish, Colin Liechty, Soroosh Noorzad, Ali Ghazizadeh Ghalati, Morteza Fayazi

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generation.

Pravallika Abbineni, Saoud Aldowaish, Colin Liechty, Soroosh Noorzad, Ali Ghazizadeh, Morteza Fayazi

CoRR, August, 2025

DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET.

Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw

IEEE J. Solid State Circuits, February, 2025

2024

Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication.

Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw

ACM Trans. Reconfigurable Technol. Syst., December, 2024

2023

AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach.

Morteza Fayazi, Morteza Tavakoli Taba, Ehsan Afshari, Ronald G. Dreslinski

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications.

Serafina Kamp, Morteza Fayazi, Zineb Benameur-El Youbi, Shuyan Yu, Ronald G. Dreslinski

CoRR, 2023

FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method.

Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging.

Morteza Tavakoli Taba, S. M. Hossein Naghavi, Morteza Fayazi, Ali Sadeghi, Andreia Cathelin, Ehsan Afshari

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks.

Morteza Fayazi, Zachary Colter, Zineb Benameur-El Youbi, Javad Bagherzadeh, Tutu Ajayi, Ronald G. Dreslinski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.

Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim

IEEE J. Solid State Circuits, 2022

Tablext: A combined neural network and heuristic based table extractor.

Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski

Array, 2022

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.

Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review.

Morteza Fayazi, Zachary Colter, Ehsan Afshari, Ronald G. Dreslinski

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.

Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.

Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff

Proceedings of the VLSI-SoC: Design Trends, 2020

An Open-source Framework for Autonomous SoC Design with Analog Block Generation.

Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2019

A Simplified Approach to Two-Port Analysis in Feedback.

Morteza Fayazi, Ali Fotowat, Zahra Kavehvash

CoRR, 2019

2017

Structural relations between brain-behavioral systems, social anxiety, depression and internet addiction: With regard to revised Reinforcement Sensitivity Theory (r-RST).

Morteza Fayazi, Jafar Hasani

Comput. Hum. Behav., 2017