Yilong Zhao

According to our database, Yilong Zhao authored at least 23 papers between 2019 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

BLADE: Boosting LLM Decoding's Communication Efficiency in DRAM-based PIM.

Yilong Zhao, Fangxin Liu, Zongwu Wang, Mingjian Li, Mingxing Zhang, Chixiao Chen, Li Jiang

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

PUSHtap: PIM-based In-Memory HTAP with Unified Data Storage Format.

Yilong Zhao, Mingyu Gao, Huanchen Zhang, Fangxin Liu, Gongye Chen, He Xian, Haibing Guan, Li Jiang

CoRR, August, 2025

PLAIN: Leveraging High Internal Bandwidth in PIM for Accelerating Large Language Model Inference via Mixed-Precision Quantization.

Yiwei Hu, Fangxin Liu, Zongwu Wang, Yilong Zhao, Tao Yang, Li Jiang, Haibing Guan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

PUSHtap: PIM-based In-Memory HTAP with Unified Data Storage Format.

Yilong Zhao, Mingyu Gao, Huanchen Zhang, Fangxin Liu, Gongye Chen, He Xian, Haibing Guan, Li Jiang

Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

STAMP: Accelerating Second-Order DNN Training Via ReRAM-Based Processing-in-Memory Architecture.

Yilong Zhao, Fangxin Liu, Mingyu Gao, Xiaoyao Liang, Qidong Tang, Chengyang Gu, Tao Yang, Naifeng Jing, Li Jiang

Proceedings of the Advanced Parallel Processing Technologies, 2025

2024

UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space.

Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, Li Jiang

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture.

Tao Yang, Fei Ma, Xiaoling Li, Fangxin Liu, Yilong Zhao, Zhezhi He, Li Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs.

Tao Yang, Dongyue Li, Fei Ma, Zhuoran Song, Yilong Zhao, Jiaxi Zhang, Fangxin Liu, Li Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy.

Tao Yang, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun, Li Jiang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization.

Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yilong Zhao, Tao Yang, Yiran Chen, Li Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals.

Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang

IEEE Trans. Computers, 2022

RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN.

Yilong Zhao, Li Jiang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Fangxin Liu, Tao Yang, Xiaoyao Liang

CoRR, 2022

DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture.

Tao Yang, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, Li Jiang

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.

Yanan Sun, Chang Ma, Zhi Li, Yilong Zhao, Jiachen Jiang, Weikang Qian, Rui Yang, Zhezhi He, Li Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.

Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang

CoRR, 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.

Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, Li Jiang

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.

Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, Li Jiang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.

Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation.

Ziqi Meng, Weikang Qian, Yilong Zhao, Yanan Sun, Rui Yang, Li Jiang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration.

Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, Li Jiang

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory.

Zhuoran Song, Yilong Zhao, Yanan Sun, Xiaoyao Liang, Li Jiang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture.

Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM.

Geng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, Yanzhi Wang

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019