Michael Papamichael

Affiliations:
  • Carnegie Mellon University, Pittsburgh, USA


According to our database1, Michael Papamichael authored at least 23 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
REPS: Recycling Entropies for Packet Spraying to Adaptively Explore Paths and Mitigate Failures.
CoRR, 2024

SMaRTT-REPS: Sender-based Marked Rapidly-adapting Trimmed & Timed Transport with Recycled Entropies.
CoRR, 2024

2019
Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor.
IEEE Micro, 2019

2018
Serving DNNs in Real Time at Datacenter Scale with Project Brainwave.
IEEE Micro, 2018

A Configurable Cloud-Scale DNN Processor for Real-Time AI.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
Configurable Clouds.
IEEE Micro, 2017

HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
A cloud-scale acceleration architecture.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016


2015
The CONNECT Network-on-Chip Generator.
Computer, 2015

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Nautilus: fast automated IP design space search using guided genetic algorithms.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2013
Cross-platform FPGA accelerator development using CoRAM and CONNECT.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Thread Cluster Memory Scheduling.
IEEE Micro, 2011

FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations.
Proceedings of the NOCS 2011, 2011

Fast scalable FPGA-based Network-on-Chip simulation models.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

2010
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2009

2007
Prototyping Efficient Interprocessor Communication Mechanisms.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007


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