Vivek Seshadri

Rahul Sharma

Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, 2023

X-RiSAWOZ: High-Quality End-to-End Multilingual Dialogue Datasets and Few-shot Agents.

[BibT_eX]

[DOI]

Ponnurangam Kumaraguru

Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023

2022

Annotated Speech Corpus for Low Resource Indian Languages: Awadhi, Bhojpuri, Braj and Magahi.

[BibT_eX]

[DOI]

CoRR, 2022

Aksharantar: Towards building open transliteration tools for the next billion users.

[BibT_eX]

[DOI]

CoRR, 2022

Feeling Proud, Feeling Embarrassed: Experiences of Low-income Women with Crowd Work.

[BibT_eX]

[DOI]

Rama Adithya Varanasi

Proceedings of the CHI '22: CHI Conference on Human Factors in Computing Systems, New Orleans, LA, USA, 29 April 2022, 2022

2021

Multilingual and code-switching ASR challenges for low resource Indian languages.

[BibT_eX]

[DOI]

CoRR, 2021

NVOverlay: Enabling Efficient and Scalable High-Frequency Snapshotting to NVM.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

MUCS 2021: Multilingual and Code-Switching ASR Challenges for Low Resource Indian Languages.

[BibT_eX]

[DOI]

Proceedings of the Interspeech 2021, 22nd Annual Conference of the International Speech Communication Association, Brno, Czechia, 30 August, 2021

MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications.

[BibT_eX]

[DOI]

Nikhil Pratap Ghanathe

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Language Translation as a Socio-Technical System: Case-Studies of Mixed-Initiative Interactions.

[BibT_eX]

[DOI]

Proceedings of the COMPASS '21: ACM SIGCAS Conference on Computing and Sustainable Societies, Virtual Event, Australia, 28 June 2021, 2021

2020

Shiftry: RNN inference in 2KB of RAM.

[BibT_eX]

[DOI]

Aayan Kumar

Konstantinos Kanellopoulos

Rahul Sharma

Proc. ACM Program. Lang., 2020

Crowdsourcing Speech Data for Low-Resource Languages from Low-Income Workers.

[BibT_eX]

[DOI]

Proceedings of The 12th Language Resources and Evaluation Conference, 2020

The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework.

[BibT_eX]

[DOI]

Nastaran Hajinazar

Pratyush Patel

Minesh Patel

Saugata Ghose

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019

In-DRAM Bulk Bitwise Execution Engine.

[BibT_eX]

[DOI]

CoRR, 2019

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.

[BibT_eX]

[DOI]

CoRR, 2019

GesturePod: Enabling On-device Gesture-based Interaction for White Cane Users.

[BibT_eX]

[DOI]

Harsha Vardhan Simhadri

Manik Varma

Prateek Jain

Proceedings of the 32nd Annual ACM Symposium on User Interface Software and Technology, 2019

PipeDream: generalized pipeline parallelism for DNN training.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM Symposium on Operating Systems Principles, 2019

Compiling KB-sized machine learning models to tiny IoT devices.

[BibT_eX]

[DOI]

Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

Exploring Crowdsourced Work in Low-Resource Settings.

[BibT_eX]

[DOI]

Proceedings of the 2019 CHI Conference on Human Factors in Computing Systems, 2019

Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional Memory.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

PipeDream: Fast and Efficient Pipeline Parallel DNN Training.

[BibT_eX]

[DOI]

CoRR, 2018

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems.

[BibT_eX]

[DOI]

CoRR, 2018

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency.

[BibT_eX]

[DOI]

CoRR, 2018

RowClone: Accelerating Data Movement and Initialization Using DRAM.

[BibT_eX]

[DOI]

CoRR, 2018

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost.

[BibT_eX]

[DOI]

CoRR, 2018

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.

[BibT_eX]

[DOI]

CoRR, 2018

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism.

[BibT_eX]

[DOI]

CoRR, 2018

2017

Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.

[BibT_eX]

[DOI]

Gennady Pekhimenko

Proc. ACM Meas. Anal. Comput. Syst., 2017

Chapter Four - Simple Operations in Memory to Reduce Data Movement.

[BibT_eX]

[DOI]

Adv. Comput., 2017

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016

BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR.

[BibT_eX]

[DOI]

CoRR, 2016

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM.

[BibT_eX]

[DOI]

CoRR, 2016

Simple DRAM and Virtual Memory Abstractions to Enable Highly Efficient Memory Systems.

[BibT_eX]

[DOI]

CoRR, 2016

Tiered-Latency DRAM (TL-DRAM).

[BibT_eX]

[DOI]

CoRR, 2016

Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.

[BibT_eX]

[DOI]

Donghyuk Lee

Samira Manabi Khan

Lavanya Subramanian

CoRR, 2016

Adaptive-Latency DRAM (AL-DRAM).

[BibT_eX]

[DOI]

CoRR, 2016

ChargeCache: Reducing DRAM latency by exploiting row access locality.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity.

[BibT_eX]

[DOI]

CoRR, 2015

Fast Bulk Bitwise AND and OR in DRAM.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2015

The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory.

[BibT_eX]

[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses.

[BibT_eX]

[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Page overlays: an enhanced virtual memory framework to enable fine-grained memory management.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

The Dirty-Block Index.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.

[BibT_eX]

[DOI]