Yoonsoo Kim

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2022
Model Predictive Control-Based Multirotor Three-Dimensional Motion Planning with Point Cloud Obstacle.
J. Aerosp. Inf. Syst., March, 2022

2020
Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs.
IEEE Access, 2020

2017
Changes of Cyber-Attacks Techniques and Patterns after the Fourth Industrial Revolution.
Proceedings of the 5th International Conference on Future Internet of Things and Cloud Workshops, 2017

2016
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

20-Gb/s 5-V<sub>PP</sub> and 25-Gb/s 3.8-V<sub>PP</sub> Area-Efficient Modulator Drivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.36 pJ/bit, 0.025 mm<sup>2</sup>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G<sub>m</sub> Bias.
IEEE J. Solid State Circuits, 2016

2015
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
Proceedings of the Symposium on VLSI Circuits, 2015

20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
Proceedings of the ESSCIRC 2014, 2014

2013
Collision-free vehicle formation control under arbitrarily switching network topology.
Proceedings of the 12th European Control Conference, 2013

2012
Consumer Propensity and Location Analysis based Real-time Location Tracing Advertisement Service Design and Implementation - Real-time Location based Advertisement System.
Proceedings of the SIGMAP and WINSYS 2012, 2012

2011
Control Systems Lab Using a LEGO Mindstorms NXT Motor System.
IEEE Trans. Educ., 2011

2010
Bisection Algorithm of Increasing Algebraic Connectivity by Adding an Edge.
IEEE Trans. Autom. Control., 2010

2001
Efficient requantization method for INTRA MB in heterogeneous transcoding.
Proceedings of the Visual Communications and Image Processing 2001, 2001

1997
Model-based error-diffusion method for tone linearity correction in binary printers.
Proceedings of the Color Imaging: Device-Independent Color, 1997

1995
New edge-enhanced error diffusion algorithm based on the error sum criterion.
J. Electronic Imaging, 1995


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