Sungchun Jang

According to our database1, Sungchun Jang authored at least 13 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020


A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G<sub>m</sub> Bias.
IEEE J. Solid State Circuits, 2016

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits, 2015

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
Proceedings of the Symposium on VLSI Circuits, 2015

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011