Gyu-Seob Jeong

According to our database1, Gyu-Seob Jeong authored at least 28 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
A Modulo-FIR Equalizer for Wireline Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Reference Spur Reduction Techniques for a Phase-Locked Loop.
IEEE Access, 2019

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

2018
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G<sub>m</sub>-Regulated Resistive-Feedback Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 0.015-mm<sup>2</sup> Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.
Sensors, 2017

2016
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

20-Gb/s 5-V<sub>PP</sub> and 25-Gb/s 3.8-V<sub>PP</sub> Area-Efficient Modulator Drivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.36 pJ/bit, 0.025 mm<sup>2</sup>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G<sub>m</sub> Bias.
IEEE J. Solid State Circuits, 2016

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits, 2015

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
Proceedings of the Symposium on VLSI Circuits, 2015

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
Proceedings of the ESSCIRC 2014, 2014

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014


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