Yosuke Ueno

According to our database, Yosuke Ueno authored at least 10 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

SFQ counter-based precomputation for large-scale cryogenic VQE machines.

Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

CoRR, 2024

Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines.

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

IEEE Comput. Archit. Lett., 2024

2023

Circuit designs for practical-scale fault-tolerant quantum computing.

Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code.

Wang Liao, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno, Yuuki Tokunaga

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes.

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi

CoRR, 2022

QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery.

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

Path Planning and Moving Obstacle Avoidance with Neuromorphic Computing.

Motoki Sakurai, Yosuke Ueno, Masaaki Kondo

Proceedings of the IEEE International Conference on Intelligence and Safety for Robotics, 2021

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code.

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2016

A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture.

Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Suzuki, Norio Shoji

IEEE J. Solid State Circuits, 2016

10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency capture.

Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Matsumoto, Hideyuki Suzuki, Norio Shoji

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016