Youhei Umeki

According to our database, Youhei Umeki authored at least 6 papers between 2012 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.

Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

IPSJ Trans. Syst. LSI Des. Methodol., 2016

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor.

Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2016

2015

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques.

Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A negative-resistance sense amplifier for low-voltage operating STT-MRAM.

Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier.

Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2012

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.

Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Low Power Electronics and Design, 2012