Sean Safarpour

According to our database, Sean Safarpour authored at least 28 papers between 2004 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Toward Automated ECOs in FPGAs.

Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Debugging with dominance: On-the-fly RTL debug solution implications.

Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Automated debugging of SystemVerilog assertions.

Brian Keng, Sean Safarpour, Andreas G. Veneris

Proceedings of the Design, Automation and Test in Europe, 2011

From RTL to silicon: The case for automated debug.

Andreas G. Veneris, Brian Keng, Sean Safarpour

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Bounded Model Debugging.

Brian Keng, Sean Safarpour, Andreas G. Veneris

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Automated Design Debugging With Maximum Satisfiability.

Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An Automated Framework for Correction and Debug of PSL Assertions.

Brian Keng, Andreas G. Veneris, Sean Safarpour

Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Automated silicon debug data analysis techniques for a hardware data acquisition environment.

Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Managing verification error traces with bounded model debugging.

Sean Safarpour, Andreas G. Veneris, Farid N. Najm

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Automated Design Debugging With Abstraction and Refinement.

Sean Safarpour, Andreas G. Veneris

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Automated debugging with high level abstraction and refinement.

Sean Safarpour, Andreas G. Veneris

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Spatial and temporal design debug using partial MaxSAT.

Yibin Chen, Sean Safarpour, Andreas G. Veneris, João Marques-Silva

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Towards automated ECOs in FPGAs.

Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

The day Sherlock Holmes decided to do EDA.

Andreas G. Veneris, Sean Safarpour

Proceedings of the 46th Design Automation Conference, 2009

2008

Improved SAT-based Reachability Analysis with Observability Don't Cares.

Sean Safarpour, Andreas G. Veneris, Rolf Drechsler

J. Satisf. Boolean Model. Comput., 2008

2007

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.

Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Improved Design Debugging Using Maximum Satisfiability.

Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Maximum circuit activity estimation using pseudo-boolean satisfiability.

Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Trace Compaction using SAT-based Reachability Analysis.

Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Abstraction and Refinement Techniques in Automated Design Debugging.

Sean Safarpour, Andreas G. Veneris

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Integrating observability don't cares in all-solution SAT solvers.

Sean Safarpour, Andreas G. Veneris, Rolf Drechsler

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the relation between simulation-based and SAT-based diagnosis.

Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Efficient SAT-based Boolean matching for FPGA technology mapping.

Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan

Proceedings of the 43rd Design Automation Conference, 2006

2005

Post-Verification Debugging of Hierarchical Designs.

Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Utilizing don't care states in SAT-based bounded sequential problems.

Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Diagnosing multiple transition faults in the absence of timing information.

Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Debugging Sequential Circuits Using Boolean Satisfiability.

Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Managing Don't Cares in Boolean Satisfiability.

Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee

Proceedings of the 2004 Design, 2004