Yuji Oda

According to our database, Yuji Oda authored at least 4 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2008

2007

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.

Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2007

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.

Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005