Masakazu Okada
According to our database1,
Masakazu Okada
authored at least 7 papers
between 1998 and 2014.
Collaborative distances:
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Bibliography
2014
High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm<sup>2</sup> Nb Process Technology.
IEICE Trans. Electron., 2014
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors.
IEICE Trans. Electron., 2014
Sensor network system to promote energy conservation realization of energy smart school.
Proceedings of the 2014 IEEE International Conference on Pervasive Computing and Communication Workshops, 2014
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology.
IEICE Trans. Electron., 2008
2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
1998
An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI.
IEEE J. Solid State Circuits, 1998