Zhiteng Chao

According to our database, Zhiteng Chao authored at least 13 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation.

Zhiteng Chao, Feng Gu, Junying Huang, Wenjie Li, Jing Ye, Huawei Li, Xiaowei Li

ACM Trans. Design Autom. Electr. Syst., September, 2025

AssertFix: Empowering Automated Assertion Fix via Large Language Models.

Hongqin Lyu, Yunlin Du, Yonghao Wang, Zhiteng Chao, Tiancheng Wang, Huawei Li

CoRR, September, 2025

AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging.

Hongqin Lyu, Yonghao Wang, Yunlin Du, Mingyu Shi, Zhiteng Chao, Wenxing Li, Tiancheng Wang, Huawei Li

CoRR, September, 2025

DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specifications.

Yonghao Wang, Jiaxin Zhou, Hongqin Lyu, Zhiteng Chao, Tiancheng Wang, Huawei Li

CoRR, September, 2025

Extend IVerilog to Support Batch RTL Fault Simulation.

Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li

CoRR, May, 2025

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow.

Zhiteng Chao, Xindi Zhang, Junying Huang, Zizhen Liu, Yixuan Zhao, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li

Integr., 2025

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion.

Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

MOSS: Multi-Modal Representation Learning on Sequential Circuits.

Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT.

Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification.

Zhiteng Chao, Qinluan Dai, Jiale Li, Zizhen Liu, Wenxing Li, Hongqin Lyu, Jing Ye, Huawei Li, Xiaowei Li

Proceedings of the IEEE International Test Conference in Asia, 2024

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver.

Zhiteng Chao, Xindi Zhang, Junying Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT.

Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li, Jing Ye, Xiaowei Li

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2020

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER.

Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li

Proceedings of the 29th IEEE Asian Test Symposium, 2020