Zhiyuan He

According to our database1, Zhiyuan He authored at least 35 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Research Progress and Challenges on Application-Driven Adversarial Examples: A Survey.
ACM Trans. Cyber Phys. Syst., 2021

Attack-Aware Detection and Defense to Resist Adversarial Examples.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Effect of geometry on the sensing mechanism of GaN Schottky barrier diode temperature sensor.
IEICE Electron. Express, 2021

Fault Tolerant Sensorless Control Strategy With Multi-States Switching Method for In-Wheel Electric Vehicle.
IEEE Access, 2021

2020
Optimized co-scheduling of mixed-precision neural network accelerator for real-time multitasking applications.
J. Syst. Archit., 2020

A Low-Cost Image Encryption Method to Prevent Model Stealing of Deep Neural Network.
J. Circuits Syst. Comput., 2020

ArchNet: Data Hiding Model in Distributed Machine Learning System.
CoRR, 2020

Memtransistors Based on Non-Layered In<sub>2</sub>S<sub>3</sub> Two-Dimensional Thin Films With Optical-Modulated Multilevel Resistance States and Gate-Tunable Artificial Synaptic Plasticity.
IEEE Access, 2020

Improved Fast Method of Initial Rotor Position Estimation for Interior Permanent Magnet Synchronous Motor by Symmetric Pulse Voltage Injection.
IEEE Access, 2020

Economic MPC-Based Smart Home Scheduling With Comprehensive Load Types, Real-Time Tariffs, and Intermittent DERs.
IEEE Access, 2020

An Error Identification and Compensation Method of a 6-DoF Parallel Kinematic Machine.
IEEE Access, 2020

A fast and test-proven methodology of assessing RTN/fluctuation on deeply scaled nano pMOSFETs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Partial Fingerprint Verification via Spatial Transformer Networks.
Proceedings of the 2020 IEEE International Joint Conference on Biometrics, 2020

Interpretability Derived Backdoor Attacks Detection in Deep Neural Networks: Work-in-Progress.
Proceedings of the 20th International Conference on Embedded Software, 2020

Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

2019
Gradient Boosting Machine: A Survey.
CoRR, 2019

An Aggregated Model for Energy Management Considering Crowdsourcing Behaviors of Distributed Energy Resources.
IEEE Access, 2019

Lossless Compression Algorithm Based on Context Tree.
Proceedings of the ICVIP 2019: The 3rd International Conference on Video and Image Processing, 2019

2018
Improved Design and Control of FBSM MMC With Boosted AC Voltage and Reduced DC Capacitance.
IEEE Trans. Ind. Electron., 2018

Multi-view Commercial Hotness Prediction Using Context-aware Neural Network Ensemble.
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2018

Urban Perception of Commercial Activeness from Satellite Images and Streetscapes.
Proceedings of the Companion of the The Web Conference 2018 on The Web Conference 2018, 2018

Perceiving Commerial Activeness Over Satellite Images.
Proceedings of the Companion of the The Web Conference 2018 on The Web Conference 2018, 2018

Unsupervised Discovery of Object Landmarks as Structural Representations.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018

2017
Modeling and analysis of DC voltage dynamics in modular multilevel converter.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Discriminative Bimodal Networks for Visual Localization and Detection with Natural Language Queries.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017

2015
Interactive projection images generation for swept-based 3D display.
Comput. Vis. Sci., 2015

2010
Multi-temperature testing for core-based system-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
J. Electron. Test., 2008

Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A heuristic for thermal-safe SoC test scheduling.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Power constrained and defect-probability driven SoC test scheduling with test set partitioning.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Hybrid BIST Test Scheduling Based on Defect Probabilities.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004


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