Yuan Pu

According to our database, Yuan Pu authored at least 28 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

RegPlace: Regularity-Aware Placement for Full-System DNN Accelerator Designs.

Jiaxi Jiang, Yuan Pu, Mingjun Li, Yuxuan Zhao, Peiyu Liao, Zuodong Zhang, Yibo Lin, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2026

Invited: Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective.

Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, Bei Yu

Proceedings of the 2026 International Symposium on Physical Design, 2026

IncreMacro-3D: Incremental Macro Placement for Face-to-Face Stacked Memory-on-Logic 3D ICs.

Lancheng Zou, Sing Sen Ye, Shuo Yin, Yuan Pu, Jiaxi Jiang, Siting Liu, Yuxuan Zhao, Bei Yu

Proceedings of the Design, Automation & Test in Europe Conference, 2026

RATuner: Retrieval-Augmented VLSI Flow Design Parameter Tuning Framework.

Peng Xu, Ziyang Yu, Yuan Pu, Xinyun Zhang, Donger Luo, Hao Geng, Siyuan Xu, Tsung-Yi Ho, Bei Yu

Proceedings of the Design, Automation & Test in Europe Conference, 2026

Smart-PCLib: A LLM-based Multi-Agent Framework for Automated PCB Component Library Generation.

Zhaohai Di, Jindong Tu, Zhiyuan He, Yuan Pu, Jiawei Liu, Chong Tong, Tsung-Yi Ho, Bei Yu, Tinghuan Chen

Proceedings of the Design, Automation & Test in Europe Conference, 2026

MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA.

Zhenghao Chen, Yuan Pu, Hairuo Han, Yuntao Nie, Jiajun Qin, Yuhan Qin, Tairu Qiu, Zhuolun He, Jianwang Zhai, Bei Yu, Kang Zhao

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning.

Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2025

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.

Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2025

Large Language Models for EDA: Future or Mirage?

Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, Bei Yu

ACM Trans. Design Autom. Electr. Syst., November, 2025

IncreMacro: Incremental Macro Placement Refinement.

Yuan Pu, Tinghuan Chen, Zhuolun He, Jiajun Qin, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling.

Jiahao Xu, Zhuolun He, Shuo Yin, Yuan Pu, Wenjian Yu, Bei Yu

ACM Trans. Design Autom. Electr. Syst., May, 2025

UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings.

Jiajun Qin, Yuan Pu, Zhuolun He, Seunggeun Kim, David Z. Pan, Bei Yu

CoRR, May, 2025

ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling.

Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson W. K. Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

Large Language Models for EDA: From Assistants to Agents.

Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, Bei Yu

Found. Trends Electron. Des. Autom., 2025

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.

Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu

Proceedings of the 2025 International Symposium on Physical Design, 2025

Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.

Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu

Proceedings of the Thirteenth International Conference on Learning Representations, 2025

GPU Acceleration for Versatile Buffer Insertion.

Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation.

Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, Bei Yu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

DSPlacer: DSP Placement for FPGA-based CNN Accelerator.

Baohui Xie, Xinrui Zhu, Zhiyuan Lu, Yuan Pu, Tongkai Wu, Xiaofeng Zou, Bei Yu, Tinghuan Chen

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision.

Rongliang Fu, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, Junying Huang, Qiang Xu, Tsung-Yi Ho

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.

Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu

Proceedings of the 2024 International Symposium on Physical Design, 2024

IncreMacro: Incremental Macro Placement Refinement.

Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu

Proceedings of the 2024 International Symposium on Physical Design, 2024

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.

Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.

Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

NeuroSelect: Learning to Select Clauses in SAT Solvers.

Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.

Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).

Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu

Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

Restructure-Tolerant Timing Prediction via Multimodal Fusion.

Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023