Zongle Huang

According to our database, Zongle Huang authored at least 8 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

MoESD: Unveil Speculative Decoding's Potential for Accelerating Sparse MoE.

Zongle Huang, Lei Zhu, Zongyuan Zhan, Ting Hu, Weikai Mao, Xianzhi Yu, Yongpan Liu, Tianyu Zhang

CoRR, May, 2025

Enhancing Memory Efficiency in Large Language Model Training Through Chronos-aware Pipeline Parallelism.

Xinyuan Lin, Chenlu Li, Zongle Huang, Chunyu Wang, Bo Xiao, Huazhong Yang, Shishi Duan, Yongpan Liu

CoRR, March, 2025

CCE: A 28nm Content Creation Engine with Asymmetric Computing, Semantic-Driven Instruction Generation and Collision-Free Outlier Mapper for Video Generation.

Chen Tang, Zongle Huang, Wenxun Wang, Yifan He, Shupei Fan, Xiaoyu Feng, Wenyu Sun, Yongpan Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks.

Wenbin Jia, Yifan He, Xiang Li, Yixuan Xie, Zongle Huang, Wenxun Wang, Boju Chen, Yaolei Li, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

Hecaton: Training and Finetuning Large Language Models with Scalable Chiplet Systems.

Zongle Huang, Shupei Fan, Chen Tang, Xinyuan Lin, Shuwen Deng, Yongpan Liu

CoRR, 2024

A 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-Assisted Cores.

Chen Tang, Xinyuan Lin, Zongle Huang, Wenyu Sun, Hongyang Jia, Yongpan Liu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Exploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the Edge.

Liu He, Yujin Wang, Zongle Huang, Shupei Fan, Chen Tang, Shuyuan Zhang, Luchang Lei, Huazhong Yang, Yongpan Liu, Hongyang Jia

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

34.7 A 28nm 2.4Mb/mm² 6.9 - 16.3TOPS/mm² eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.

Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2024