Yaolei Li

According to our database, Yaolei Li authored at least 5 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

34.7 A 28nm 2.4Mb/mm² 6.9 - 16.3TOPS/mm² eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.

Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.

Lu Zhang, Dejun Mu, Yuxuan Huang, Jingyu Wang, Yifan He, Yaolei Li, Lizhou Liu, Kaiwei Zou, Huazhong Yang, Yongpan Liu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.

Yaolei Li, Jinshan Yue, Jingyu Wang, Chen Tang, Yifan He, Wenbin Jia, Kaiwei Zou, Lu Zhang, Huazhong Yang, Yongpan Liu

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.

Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation.

Hedi Wang, Zengwei Wang, Yaolei Li, Chen Tang, Jinxu Gao, Huazhong Yang, Yongpan Liu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023