Aiman H. ElMaleh
Affiliations: King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia
According to our database^{1},
Aiman H. ElMaleh
authored at least 61 papers
between 1992 and 2023.
Collaborative distances:
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Bibliography
2023
J. Supercomput., March, 2023
2022
FxPQNet: A PostTraining Quantizer for the Design of Mixed LowPrecision DNNs With Dynamic FixedPoint Representation.
IEEE Access, 2022
2021
Integr., 2021
2019
FPGABased Accelerators of Deep Learning Networks for Learning and Classification: A Review.
IEEE Access, 2019
2018
Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits.
J. Circuits Syst. Comput., 2018
2017
A Fault Tolerance Technique for Combinational Circuits Based on SelectiveTransistor Redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing.
Integr., 2017
A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization.
Integr., 2017
Finite state machinebased fault tolerance technique with enhanced area and power of synthesised sequential circuits.
IET Comput. Digit. Tech., 2017
2016
A lowcost platform for the prototyping and characterization of digital circuit IPs.
Integr., 2016
Majoritybased evolution state assignment algorithm for area and power optimisation of sequential circuits.
IET Comput. Digit. Tech., 2016
Appl. Intell., 2016
2015
SimulationBased Method for Synthesizing Soft Error Tolerant Combinational Circuits.
IEEE Trans. Reliab., 2015
J. Circuits Syst. Comput., 2015
State assignment for area minimization of sequential circuits based on cuckoo search optimization.
Comput. Electr. Eng., 2015
State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015
2014
A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
2013
Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits.
Appl. Soft Comput., 2013
Enhancing Reliability of Combinational Circuits against Soft Errors by Using a Generalized Modular Redundancy Scheme.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
2012
Integr., 2012
2011
Comput. Electr. Eng., 2011
2010
A scheme of test data compression based on coding of even bits marking and selective output inversion.
Comput. Electr. Eng., 2010
2009
Defecttolerant n<sup>2</sup>transistor structure for reliable nanoelectronic designs.
IET Comput. Digit. Tech., 2009
Reconfigurable broadcast scan compression using relaxationbased test vector decomposition.
IET Comput. Digit. Tech., 2009
A new collaborative scheme of test vector compression based on equalrunlength coding (ERLC).
Proceedings of the 13th International Conference on Computers Supported Cooperative Work in Design, 2009
2008
IET Comput. Digit. Tech., 2008
Test data compression for systemonachip using extended frequencydirected runlength code.
IET Comput. Digit. Tech., 2008
New Technique for Improving Performance of LDPC Codes in the Presence of Trapping Sets.
EURASIP J. Wirel. Commun. Netw., 2008
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008
2007
Efficient test compaction for combinational circuits based on Fault detection countdirected clustering.
IET Comput. Digit. Tech., 2007
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos.
Proceedings of the 16th Asian Test Symposium, 2007
2006
Efficient Static Compaction Techniques for Sequential Circuits Based on ReverseOrder Restoration and Test Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Eng. Appl. Artif. Intell., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
2003
Test vector decompositionbased static compaction algorithms for combinational circuits.
ACM Trans. Design Autom. Electr. Syst., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
On efficient extraction of partially specified test sets for synchronous sequential circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A static test compaction technique for combinational circuits based on independent fault clustering.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
An Efficient Test Relaxation Technique for Combinational & FullScan Sequential Circuits.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
An efficient test relaxation technique for combinational circuits based on critical path tracing.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Extended frequencydirected runlength code with improved application to systemonachip test data compression.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
A retimingbased test pattern generator design for builtin self test of data path architectures.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
An efficient test vector compression technique based on geometric shapes [systemonachip].
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
1998
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.
Proceedings of the 35th Conference on Design Automation, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1995
Delayfault testability preservation of the concurrent decomposition and factorization transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Des. Test Comput., 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 32st Conference on Design Automation, 1995
1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992