Cuiyun Jiang

According to our database, Cuiyun Jiang authored at least 16 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Design of approximate Booth multipliers based on error compensation.

Yongxia Sheng, Huaguo Liang, Bao Fang, Cuiyun Jiang, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu

Integr., May, 2023

2022

M-RO PUF: A portable pure digital RO PUF based on MUX unit.

Liang Yao, Huaguo Liang, Qian Han, Hong Zhang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi, Yingchun Lu

Microelectron. J., 2022

2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.

Bao Fang, Huaguo Liang, Dawen Xu, Maoxiang Yi, Yongxia Sheng, Cuiyun Jiang, Zhengfeng Huang, Yingchun Lu

Integr., 2021

A N: 1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs.

Huaguo Liang, Danqing Li, Zhao Yang, Tianming Ni, Zhengfeng Huang, Cuiyun Jiang

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

Jitter-Quantizing-Based TRNG Robust Against PVT Variations.

Yingchun Lu, Huaguo Liang, Liang Yao, Xinyu Wang, Haochen Qi, Maoxiang Yi, Cuiyun Jiang, Zhengfeng Huang

IEEE Access, 2020

2019

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.

Maoxiang Yi, Jingchang Bian, Tianming Ni, Cuiyun Jiang, Hao Chang, Huaguo Liang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017

A highly reliable butterfly PUF in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yingchun Lu, Aibin Yan, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

2016

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.

Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xuejun Li

Microelectron. Reliab., 2016

2015

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi

IEICE Trans. Electron., 2015

2010

A scheme of test data compression based on coding of even bits marking and selective output inversion.

Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh

Comput. Electr. Eng., 2010

2009

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding.

Huaguo Liang, Wenfa Zhan, Qiang Luo, Cuiyun Jiang

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing.

Maoxiang Yi, Huaguo Liang, Kaihua Zhan, Cuiyun Jiang

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2007

Block Marking and Updating Coding in Test Data Compression for SoC.

Lei Zhang, Huaguo Liang, Wenfa Zhan, Cuiyun Jiang

Proceedings of the 16th Asian Test Symposium, 2007

2005

A BIST Scheme Based on Selecting State Generation of Folding Counters.

Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003

Sharing BIST with Multiple Cores for System-on-a-Chip.

Huaguo Liang, Cuiyun Jiang

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003