Alessandro Ottaviano

Orcid: 0009-0000-9924-3536

According to our database1, Alessandro Ottaviano authored at least 10 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.
Int. J. Parallel Program., April, 2024

A High-Performance, Energy-Efficient Modular DMA Engine Architecture.
IEEE Trans. Computers, January, 2024

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation.
CoRR, 2024

2023
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.
CoRR, 2023

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.
CoRR, 2023

CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers.
CoRR, 2023

Towards a RISC-V Open Platform for Next-generation Automotive ECUs.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

2022
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022


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