Alexander Czutro

According to our database1, Alexander Czutro authored at least 24 papers between 2005 and 2014.

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Bibliography

2014
SAT-Based Test Pattern Generation with Improved Dynamic Compaction.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Variation-aware deterministic ATPG.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Efficiency and applications of SAT-based test pattern generation: complex fault models and optimisation problems.
PhD thesis, 2013

SAT-Based Analysis of Sensitizable Paths.
IEEE Des. Test, 2013

2012
SAT-ATPG using preferences for improved detection of complex defect mechanisms.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.
Proceedings of the 25th International Conference on VLSI Design, 2012

Functional test of small-delay faults using SAT and Craig interpolation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Small-delay-fault ATPG with waveform accuracy.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

On the quality of test vectors for post-silicon characterization.
Proceedings of the 17th IEEE European Test Symposium, 2012

Multi-conditional SAT-ATPG for power-droop testing.
Proceedings of the 17th IEEE European Test Symposium, 2012

#SAT-based vulnerability analysis of security components - A case study.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

On the optimality of K longest path generation algorithm under memory constraints.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Variation-Aware Fault Grading.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Estimation of component criticality in early design steps.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

SAT-based analysis of sensitisable paths.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Efficient SAT-Based Search for Longest Sensitisable Paths.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.
Int. J. Parallel Program., 2010

2009
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

ATPG-based grading of strong fault-secureness.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Dynamic Compaction in SAT-Based ATPG.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.
Proceedings of the 13th European Test Symposium, 2008

2007
Power Droop Testing.
IEEE Des. Test Comput., 2007

2005
Evolutionary Optimization in Code-Based Test Compression.
Proceedings of the 2005 Design, 2005


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