Mariane Comte

According to our database1, Mariane Comte authored at least 47 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits.
J. Electron. Test., April, 2023

2021
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit.
J. Electron. Test., 2021

Exploring on-line RF performance monitoring based on the indirect test strategy.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

2020
Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits.
J. Electron. Test., 2020

Implementing indirect test of RF circuits without compromising test quality: a practical case study.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies.
J. Electron. Test., 2019

Which metrics to use for RF indirect test strategy?
Proceedings of the 16th International Conference on Synthesis, 2019

Use of ensemble methods for indirect test of RF circuits: can it bring benefits?
Proceedings of the IEEE Latin American Test Symposium, 2019

2018
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies.
J. Electron. Test., 2017

Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era.
ACM J. Emerg. Technol. Comput. Syst., 2016

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect.
Proceedings of the 17th Latin-American Test Symposium, 2016

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies.
Microelectron. J., 2015

A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Toward Adaptation of ADCs to Operating Conditions through On-chip Correction.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements.
Microelectron. J., 2014

Testing for gate oxide short defects using the detectability interval paradigm.
it Inf. Technol., 2014

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing.
Proceedings of the 15th Latin American Test Workshop, 2014

Solutions for the self-adaptation of communicating systems in operation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

New implementions of predictive alternate analog/RF test with augmented model redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.
Microelectron. J., 2013

Accurate and efficient analytical electrical model of antenna for NFC applications.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.
Proceedings of the 14th Latin American Test Workshop, 2013

Implementing model redundancy in predictive alternate test to improve test confidence.
Proceedings of the 18th IEEE European Test Symposium, 2013

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Smart selection of indirect parameters for DC-based alternate RF IC testing.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Making predictive analog/RF alternate test strategy independent of training set size.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics.
J. Electron. Test., 2011

2009
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A multi-converter DFT technique for complex SIP: Concepts and validation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator.
VLSI Design, 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.
Proceedings of the 13th European Test Symposium, 2008

2007
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC.
IET Comput. Digit. Tech., 2007

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Proceedings of the 12th European Test Symposium, 2007

2006
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.
IEEE Des. Test Comput., 2006

Electrical Behavior of GOS Fault affected Domino Logic Cell.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
J. Electron. Test., 2005

2004
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.
J. Electron. Test., 2004

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
J. Electron. Test., 2004

2003
A-to-D converters static error detection from dynamic parameter measurement.
Microelectron. J., 2003

A New Methodology For ADC Test Flow Optimization.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Estimating Static Parameters of A-to-D Converters from Spectral Analysis.
Proceedings of the 3rd Latin American Test Workshop, 2002


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