Piet Engelke

According to our database1, Piet Engelke authored at least 29 papers between 2000 and 2017.

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Bibliography

2017
BASTION: Board and SoC test instrumentation for ageing and no failure found.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Struktureller Test im System.
Proceedings of the Aspekte der Technischen Informatik, 2014

2013
On the feasibility of combining on-line-test and self repair for logic circuits.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Funding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehicles.
Proceedings of the 17th IEEE European Test Symposium, 2012

Scan Based Tests via Standard Interfaces.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2010
Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.
Int. J. Parallel Program., 2010

2009
SUPERB: Simulator utilizing parallel evaluation of resistive bridges.
ACM Trans. Design Autom. Electr. Syst., 2009

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Dynamic Compaction in SAT-Based ATPG.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Automatic Test Pattern Generation for Interconnect Open Defects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.
Proceedings of the 13th European Test Symposium, 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Resistive Bridging Fault Simulation of Industrial Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

2006
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Simulating Resistive-Bridging and Stuck-At Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Automatic Test Pattern Generation for Resistive Bridging Faults.
J. Electron. Test., 2006

2005
Modeling Feedback Bridging Faults with Non-Zero Resistance.
J. Electron. Test., 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A unified fault model and test generation procedure for interconnect opens and bridges.
Proceedings of the 10th European Test Symposium, 2005

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2000
A parameterizable fault simulator for bridging faults.
Proceedings of the 5th European Test Workshop, 2000


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