Ameer Abdelhadi

According to our database1, Ameer Abdelhadi authored at least 27 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

Atalanta: A Bit is Worth a "Thousand" Tensor Values.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging.
IEEE J. Solid State Circuits, November, 2023

2022
Schrödinger's FP: Dynamic Adaptation of Floating-Point Containers for Deep Learning Training.
CoRR, 2022

A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

A Massive-Scale Brain Activity Decoding Chip.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

2021
Adversarial Hardware With Functional and Topological Camouflage.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Boveda: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick.
Proceedings of Machine Learning and Systems 2021, 2021

Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Reconfigurable Synthesizable Synchronization FIFOs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

2019
Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Modular Switched Multiported SRAM-Based Memories.
ACM Trans. Reconfigurable Technol. Syst., 2016

A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Modular SRAM-Based Binary Content-Addressable Memories.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Deep and narrow binary content-addressable memories using FPGA-based BRAMs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Modular multi-ported SRAM-based memories.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks.
Integr., 2013

Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
Timing-driven variation-aware nonuniform clock mesh synthesis.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010


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