Mark R. Greenstreet

According to our database1, Mark R. Greenstreet authored at least 75 papers between 1987 and 2020.

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Bibliography

2020
Optimization and Comparison of Synchronizers.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
Integrating SMT with Theorem Proving for Verification of Analog and Mixed-Signal Circuits (Invited Tutorial).
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

Finding All DC Operating Points Using Interval Arithmetic Based Verification Algorithms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Verifying Timed, Asynchronous Circuits using ACL2.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
Smtlink 2.0.
Proceedings of the 15th International Workshop on the ACL2 Theorem Prover and Its Applications, 2018

Convex Functions in ACL2(r).
Proceedings of the 15th International Workshop on the ACL2 Theorem Prover and Its Applications, 2018

Real Vector Spaces and the Cauchy-Schwarz Inequality in ACL2(r).
Proceedings of the 15th International Workshop on the ACL2 Theorem Prover and Its Applications, 2018

Explaining Metastability in Real Synchronizers.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Finding Glitches Using Formal Methods.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Extending ACL2 with SMT Solvers.
Proceedings of the Proceedings Thirteenth International Workshop on the ACL2 Theorem Prover and Its Applications, 2015

Integrating SMT with Theorem Proving for Analog/Mixed-Signal Circuit Verification.
Proceedings of the NASA Formal Methods - 7th International Symposium, 2015

2014
Verifying global start-up for a Möbius ring-oscillator.
Formal Methods Syst. Des., 2014

Response property checking via distributed state space exploration.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

2013
Verifying global convergence for a digital phase-locked loop.
Proceedings of the Formal Methods in Computer-Aided Design, 2013

Distributed Explicit State Model Checking of Deadlock Freedom.
Proceedings of the Computer Aided Verification - 25th International Conference, 2013

2012
Modeling Energy-Time Trade-Offs in VLSI Computation.
IEEE Trans. Computers, 2012

Oscillator verification with probability one.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

2011
On the Energy Complexity of Parallel Algorithms.
Proceedings of the International Conference on Parallel Processing, 2011

Parameterized verification of deadlock freedom in symmetric cache coherence protocols.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

Synchronizer Performance in Deep Sub-Micron Technology.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
Varactor-based signal restoration for near-speed-of-light surfing global interconnect.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Formal Verification of an Arbiter Circuit.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A modular synchronizing FIFO for NoCs.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Verifying VLSI Circuits.
Proceedings of the Automated Technology for Verification and Analysis, 2009

Synchronizer Behavior and Analysis.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Practical Asynchronous Interconnect Network Design.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Energy Optimal Scheduling on Multiprocessors with Migration.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Verifying start-up conditions for a ring oscillator.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Verifying an Arbiter Circuit.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

Faster projection based methods for circuit level verification.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
An efficient linear programming solver for optimal filter synthesis.
Numer. Linear Algebra Appl., 2007

Surfing Pipelines: Theory and Implementation.
IEEE J. Solid State Circuits, 2007

A Survey and Taxonomy of GALS Design Styles.
IEEE Des. Test Comput., 2007

Circuit Level Verification of a High-Speed Toggle.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Computing synchronizer failure probabilities.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Simulating Improbable Events.
Proceedings of the 44th Design Automation Conference, 2007

A Jitter Attenuating Timing Chain.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
System-on-Chip: Reuse and Integration.
Proc. IEEE, 2006

Analysing the Robustness of Surfing Circuits.
Electron. Notes Theor. Comput. Sci., 2006

Surfing Interconnect.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Noise margin analysis for dynamic logic circuits.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A unified optimization framework for equalization filter synthesis.
Proceedings of the 42nd Design Automation Conference, 2005

Energy Efficient Surfing.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
Crosstalk Cancellation for Realistic PCB Buses.
Proceedings of the Integrated Circuit and System Design, 2004

A Signal Integrity Test Bed for PCB Buses.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Surfing: a robust form of wave pipelining using self-timed circuit techniques.
Microprocess. Microsystems, 2003

Equalizing Filter Design for Crosstalk Cancellation.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Synthesizing optimal filters for crosstalk-cancellation for high-speed buses.
Proceedings of the 40th Design Automation Conference, 2003

Efficient Self-Timed Interfaces for Crossing Clock Domains.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
An Event Spacing Experiment.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

A Negative-Overhead, Self-Timed Pipeline.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
A light-weight framework for hardware verification.
Int. J. Softw. Tools Technol. Transf., 2001

Temporal Properties of Self-Timed Rings.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

How to Achieve Worst-Case Performance.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

1999
Formal verification in hardware design: a survey.
ACM Trans. Design Autom. Electr. Syst., 1999

Reachability Analysis Using Polygonal Projections.
Proceedings of the Hybrid Systems: Computation and Control, Second International Workshop, 1999

A Fast, asP*, RGD Arbiter.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

Real-Time Merging.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Integrating Projections.
Proceedings of the Hybrid Systems: Computation and Control, First International Workshop, 1998

Verifying a Self-Timed Divider.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
Self-Timed Meshes Are Faster Than Synchronous.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
Verifying Safety Properties of Differential Equations.
Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995
Automatic Verification of Asynchronous Circuits.
IEEE Des. Test Comput., 1995

Implementing a STARI chip.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
Automatic Verification of Refinement.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

How fast will the flip flop?
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1992
Using Synchronized Transitions for Simulation and Timing Verification.
Proceedings of the Designing Correct Circuits, 1992

1990
Bubbles can make self-timed pipelines fast.
J. VLSI Signal Process., 1990

1988
From High-Level Descriptions to VLSI Circuits.
BIT, 1988

1987
VLSI with a very low scale investment.
Integr., 1987


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