Amir Masoud Gharehbaghi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2020

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints.

[BibT_eX]

[DOI]

Akihiro Goda

Yukio Miyasaka

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme.

[BibT_eX]

[DOI]

Heming Sun

Zhengxue Cheng

Shinji Kimura

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Signal Selection Methods for Debugging Gate-Level Sequential Circuits.

[BibT_eX]

[DOI]

Yusuke Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Approximate Arithmetic Circuit Design Using a Fast and Scalable Method.

[BibT_eX]

[DOI]

Qi Lu

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

High-Level Engineering Change Through Programmable Datapath and SMT Solvers.

[BibT_eX]

[DOI]

Qinhao Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints.

[BibT_eX]

[DOI]

Tomohiro Maruoka

Yukio Miyasaka

Akihiro Goda

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Signal Selection Methods for Efficient Multi-Target Correction.

[BibT_eX]

[DOI]

Yusuke Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults.

[BibT_eX]

[DOI]

Conrad J. Moore

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

C Description Reconstruction Method from a Revised Netlist for ECO Support.

[BibT_eX]

[DOI]

Yusuke Kimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A New Reconfigurable Architecture with Applications to IoT and Mobile Computing.

[BibT_eX]

[DOI]

Tomohiro Maruoka

Proceedings of the Internet of Things. Information Processing in an Increasingly Connected World, 2018

2017

A new approach for constructing logic functions after ECO.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A new approach for selecting inputs of logic functions during debug.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A low-cost approximate 32-point transform architecture.

[BibT_eX]

[DOI]

Heming Sun

Zhengxue Cheng

Shinji Kimura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.

[BibT_eX]

[DOI]

Conrad J. Moore

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A new approach for diagnosing bridging faults in logic designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Post Silicon Debugging of Electrical Bugs Using Trace Buffers.

[BibT_eX]

[DOI]

Kentaro Iwata

Mehdi Baradaran Tahoori

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Fast and Efficient Signature-Based Sub-Circuit Matching.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Efficient signature-based sub-circuit matching.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Trace signal selection methods for post silicon debugging.

[BibT_eX]

[DOI]

Shridhar Choudhary

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

2014

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Specification and formal verification of power gating in processors.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

Debugging processors with advanced features by reprogramming LUTs on FPGA.

[BibT_eX]

[DOI]

Satoshi Jo

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).

[BibT_eX]

[DOI]

Satoshi Jo

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

Transaction Ordering in Network-on-Chips for Post-Silicon Validation.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Transaction-based post-silicon debug of many-core System-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Automatic rectification of design errors in complex processors with programmable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Global transaction ordering in Network-on-Chips for post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Formal verification guided automatic design error diagnosis and correction of complex processors.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2010

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).

[BibT_eX]

[DOI]

Bijan Alizadeh

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Pipelined Microprocessors Optimization and Debugging.

[BibT_eX]

[DOI]

Bijan Alizadeh

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Transaction-based debugging of system-on-chips with patterns.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Debugging from high level down to gate level.

[BibT_eX]

[DOI]

Yoshihisa Kojima

Proceedings of the 46th Design Automation Conference, 2009

2008

Timing verification of distributed network systems at higher levels of abstraction.

[BibT_eX]

[DOI]

Hassan Hatefi-Ardakani

Shaahin Hessabi

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

System-Level Assertion-Based Performance Verification for Embedded Systems.

[BibT_eX]

[DOI]

Hassan Hatefi-Ardakani

Shaahin Hessabi

Proceedings of the Advances in Computer Science and Engineering, 2008

2007

An assertion-based verification methodology for system-level design.

[BibT_eX]

[DOI]