Yukio Miyasaka

According to our database, Yukio Miyasaka authored at least 11 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams.

Jitendra Kumar, Yukio Miyasaka, Asutosh Srivastava, Masahiro Fujita

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

2022

Parallel Scheduling Attention Mechanism: Generalization and Optimization.

Mingfei Yu, Yukio Miyasaka, Masahiro Fujita

IPSJ Trans. Syst. LSI Des. Methodol., 2022

2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Logic Synthesis for Generalization and Learning Addition.

Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication.

Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita

IPSJ Trans. Syst. LSI Des. Methodol., 2020

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays.

Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek

Proceedings of the VLSI-SoC: Design Trends, 2020

SAT-Based Data-Flow Mapping Onto Array Processor.

Yukio Miyasaka, Masahiro Fujita

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints.

Akihiro Goda, Yukio Miyasaka, Amir Masoud Gharehbaghi, Masahiro Fujita

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations.

Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing.

Yukio Miyasaka, Ashish Mittal, Masahiro Fujita

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints.

Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi, Masahiro Fujita

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019