Andrei Radulescu

According to our database1, Andrei Radulescu authored at least 32 papers between 1998 and 2021.

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Bibliography

2021
Developing and Applying Custom Static Analysis Tools for Industrial Multi-Language Code Bases.
Proceedings of the 20th Belgium-Netherlands Software Evolution Workshop, 2021

2018
Model-based software restructuring: Lessons from cleaning up COM interfaces in industrial legacy code.
Proceedings of the 25th International Conference on Software Analysis, 2018

2016
Industrial Software Rejuvenation Using Open-Source Parsers.
Proceedings of the Theory and Practice of Model Transformations, 2016

2010
Embedded Network Protocols for Mobile Devices.
Proceedings of the Formal Methods for Industrial Critical Systems, 2010

2007
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic.
VLSI Design, 2007

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip.
VLSI Design, 2007

2006
Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

NoC monitoring: impact on the design flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A methodology for mapping multiple use-cases onto networks on chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Mapping and configuration methods for multi-use-case networks on chips.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
An event-based monitoring service for networks on chip.
ACM Trans. Design Autom. Electr. Syst., 2005

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Æthereal Network on Chip: Concepts, Architectures, and Implementations.
IEEE Des. Test Comput., 2005

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.
Proceedings of the 2005 Design, 2005

A unified approach to constrained mapping and routing on network-on-chip architectures.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Deadlock Prevention in the Æthereal Protocol.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
An event-based network-on-chip monitoring service.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
Proceedings of the 2004 Design, 2004

Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach.
Proceedings of the 2004 Design, 2004

2003
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
Proceedings of the 2003 Design, 2003

Guaranteeing the Quality of Services in Networks on Chip.
Proceedings of the Networks on Chip, 2003

2002
Low-Cost Task Scheduling for Distributed-Memory Machines.
IEEE Trans. Parallel Distributed Syst., 2002

2001
CPR: Mixed Task and Data Parallel Scheduling for Distributed Systems.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

A Low-Cost Approach towards Mixed Task and Data Parallel Scheduling.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

2000
The Distributed ASCI Supercomputer Project.
ACM SIGOPS Oper. Syst. Rev., 2000

Fast and Effective Task Scheduling in Heterogeneous Systems.
Proceedings of the 9th Heterogeneous Computing Workshop, 2000

Preemptive Task Scheduling for Distributed Systems (Research Note).
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
LLB: A Fast and Effective Scheduling Algorithm for Distributed-Memory Systems.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

On the complexity of list scheduling algorithms for distributed-memory systems.
Proceedings of the 13th international conference on Supercomputing, 1999

FLB: Fast Load Balancing for Distributed-Memory Machines.
Proceedings of the International Conference on Parallel Processing 1999, 1999

1998
GLB: a low-cost scheduling algorithm for distributed-memory architectures.
Proceedings of the 5th International Conference On High Performance Computing, 1998


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