Peter M. W. Knijnenburg

According to our database1, Peter M. W. Knijnenburg authored at least 42 papers between 1991 and 2007.

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Bibliography

2007
On the Problem of Minimizing Workload Execution Time in SMT Processors.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Strategies for Compiling µ TC to Novel Chip Multiprocessors.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Predictable Performance in SMT Processors: Synergy between the OS and SMTs.
IEEE Trans. Computers, 2006

Special Issue: 10th International Workshop on Compilers for Parallel Computers (CPC 2003).
Concurrency and Computation: Practice and Experience, 2006

UFS: a global trade-off strategy for loop unrolling for VLIW architectures.
Concurrency and Computation: Practice and Experience, 2006

Code Size Reduction by Compiler Tuning.
Proceedings of the Embedded Computer Systems: Architectures, 2006

On the impact of data input sets on statistical compiler tuning.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Generating new general compiler optimization settings.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Optimizing general purpose compiler optimization.
Proceedings of the Second Conference on Computing Frontiers, 2005

Architectural support for real-time task scheduling in SMT processors.
Proceedings of the 2005 International Conference on Compilers, 2005

Automatic Selection of Compiler Options Using Non-parametric Inferential Statistics.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
QoS for High-Performance SMT Processors in Embedded Systems.
IEEE Micro, 2004

The effect of cache models on iterative compilation for combined tiling and unrolling.
Concurrency and Computation: Practice and Experience, 2004

Statistical Selection of Compiler Options.
Proceedings of the 12th International Workshop on Modeling, 2004

Enabling SMT for real-time embedded systems.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Feasibility of QoS for SMT.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Implicit vs. Explicit Resource Allocation in SMT Processors.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Predictable performance in SMT processors.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.
The Journal of Supercomputing, 2003

2002
Integrating Loop and Data Transformations for Global Optimization.
J. Parallel Distributed Comput., 2002

Iterative Compilation.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Evaluating Iterative Compilation.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

2001
Cache Models for Iterative Compilation.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000
The Distributed ASCI Supercomputer Project.
Operating Systems Review, 2000

1999
Nonsingular Data Transformations: Definition, Validity, and Applications.
International Journal of Parallel Programming, 1999

A Feasibility Study in Iterative Compilation.
Proceedings of the High Performance Computing, Second International Symposium, 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Efficient Parallelization Using Combined Loop and Data Transformations.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
The Automatic Generation of Sparse Primitives.
ACM Trans. Math. Softw., 1998

Efficient implementation of the row-column 8×8 IDCT on VLIW architectures.
Proceedings of the 9th European Signal Processing Conference, 1998


1997
The Semantics of the Combination of Atomized Statements and Parallel Choice.
Formal Asp. Comput., 1997

Non-Singular Data Transformations: Definition, Validity and Applications.
Proceedings of the 11th international conference on Supercomputing, 1997


1996
A Note on the Smyth Powerdomain Construction.
Fundam. Inform., 1996

1994
Partial Hyperdoctrines: Categorical Models for Partial Function Logic and Hoare Logic.
Mathematical Structures in Computer Science, 1994

Reshaping Access Patterns for Generating Sparse Codes.
Proceedings of the Languages and Compilers for Parallel Computing, 1994

1993
Divergence Models for Atomized Statements and Parallel Choice.
Proceedings of the Second Israel Symposium on Theory of Computing Systems, 1993

1992
A Categorical Interpretation of Partial Function Logic and Hoare Logic.
Proceedings of the Logical Foundations of Computer Science, 1992

1991
On Models for Propositional Dynamic Logic.
Theor. Comput. Sci., 1991

On the Semantics of Atomized Statements - the Parallel-Choice Option (Extended Abstract).
Proceedings of the Fundamentals of Computation Theory, 8th International Symposium, 1991


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