Jinil Chung
Orcid: 0000-0002-2306-9735
According to our database1,
Jinil Chung
authored at least 9 papers
between 2014 and 2021.
Collaborative distances:
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Bibliography
2021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits, 2021
2020
IEEE Access, 2020
2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014