Arne Symons

Orcid: 0000-0002-4595-9384

According to our database1, Arne Symons authored at least 15 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Fine-Grained Fusion: The Missing Piece in Area-Efficient State Space Model Acceleration.
CoRR, April, 2025

Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators.
IEEE Trans. Computers, January, 2025

Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices.
CoRR, 2024

Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Hardware-aware NAS by Genetic Optimisation with a Design Space Exploration Simulator.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
DeFiNES: A DSE Framework Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators.
Dataset, November, 2022

Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks.
CoRR, 2022

2021
LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021


  Loading...