Arne Symons
Orcid: 0000-0002-4595-9384
According to our database1,
Arne Symons authored at least 18 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026
MONET: Modeling and Optimization of neural NEtwork Training from Edge to Data Centers.
CoRR, March, 2026
2025
Hardware-aware Neural Architecture Search of Early Exiting Networks on Edge Accelerators.
CoRR, December, 2025
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2025
Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators.
IEEE Trans. Computers, January, 2025
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Fine-Grained Fusion: The Missing Piece in Area-Efficient State Space Model Acceleration.
Proceedings of the 34th International Conference on Parallel Architectures and Compilation Techniques, 2025
2024
Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
2023
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Hardware-aware NAS by Genetic Optimisation with a Design Space Exploration Simulator.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
DeFiNES: A DSE Framework Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators.
Dataset, November, 2022
Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks.
CoRR, 2022
2021
LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021