Debabrata Mohapatra

According to our database1, Debabrata Mohapatra authored at least 20 papers between 2007 and 2022.

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Bibliography

2022
XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.
CoRR, 2022

2021
Design Considerations for Edge Neural Network Accelerators: An Industry Perspective.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2014
Scalable Effort Hardware Design.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Low-Power Digital Signal Processing Using Approximate Adders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Energy-efficient recognition and mining processor using scalable effort design.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems.
J. Signal Process. Syst., 2012

Empirical Evidence Against CAPM: Relating Alphas and Returns to Betas.
IEEE J. Sel. Top. Signal Process., 2012

2011
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2011

IMPACT: imprecise adders for low-power approximate computing.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Design of voltage-scalable meta-functions for approximate computing.
Proceedings of the Design, Automation and Test in Europe, 2011

Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2010

VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture.
Proceedings of the 28th International Conference on Computer Design, 2010

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
Proceedings of the 47th Design Automation Conference, 2010

2009
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.
Proceedings of the 46th Design Automation Conference, 2009

2007
Low-power process-variation tolerant arithmetic units using input-based elastic clocking.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007


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