Philippe Magarshack

According to our database1, Philippe Magarshack authored at least 22 papers between 2001 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
Breakthrough technologies and reference designs for new IoT applications.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.
IEEE J. Solid State Circuits, 2014


Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Gaining 10x in energy efficiency in the next decade in consumer products.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
Beyond the horizon: The next 10x reduction in power - Challenges and solutions.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
3-D stacked die: now or future?
Proceedings of the 47th Design Automation Conference, 2010

2009
Low-Power Design Solutions forWireless Multimedia SoCs.
IEEE Des. Test Comput., 2009

2007
Design challenges in 45nm and below: DFM, low-power and design for reliability.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

DFM/DFY: should you trust the surgeon or the family doctor?
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
"The IC nanometer race -- what will it take to win?".
Proceedings of the 43rd Design Automation Conference, 2006

2004
Guest Editors' Introduction: Design for Yield and Reliability.
IEEE Des. Test Comput., 2004

2003
Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

System-on-chip beyond the nanometer wall.
Proceedings of the 40th Design Automation Conference, 2003

Fast, cheap and under control: the next implementation fabric.
Proceedings of the 40th Design Automation Conference, 2003

2002
Improving SoC Design Quality through a Reproducible Design Flow.
IEEE Des. Test Comput., 2002

SoC's Trends and Challenges going to 0.10µm.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Systems-on-chip needs for embedded software development: an industrial perspective.
Proceedings of the 2002 Joint Conference on Languages, 2002

2001
Quality of SoC Designs through Quality of the Design Flow: Status and Needs.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Design challenges and emerging EDA solutions in mixed-signal IC design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?
Proceedings of the 38th Design Automation Conference, 2001


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