Mohammad Hosseinabady

According to our database1, Mohammad Hosseinabady authored at least 48 papers between 2003 and 2020.

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Bibliography

2020
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip.
CoRR, 2020

Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.
Proceedings of the PARMA-DITAM@HiPEAC 2020: 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020

Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System.
Proceedings of the PARMA-DITAM@HiPEAC 2020: 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020

2019
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019

Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019

Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities.
CoRR, 2019

2018
Dynamic Energy Management of FPGA Accelerators in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2018

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR, 2018

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Multi-precision convolutional neural networks on heterogeneous hardware.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.
Proceedings of the Parallel Computing is Everywhere, 2017

Pipelined Streaming Computation of Histogram in FPGA OpenCL.
Proceedings of the Parallel Computing is Everywhere, 2017

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling.
IEEE Trans. Computers, 2016

2015
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Energy optimization of FPGA-based stream-oriented computing with power gating.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Run-time power gating in hybrid ARM-FPGA devices.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2012
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation.
IET Comput. Digit. Tech., 2012

Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.
IET Comput. Digit. Tech., 2012

Exploring dynamically reconfigurable multicore designs with NoRC designer.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

2011
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Single-Event Transient Analysis in High Speed Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

2010
Task Dispersal Measurement in Dynamic Reconfigurable NoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Effective modelling of large NoCs using SystemC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SystemC Architectural Transaction Level Modelling for Large NoCs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009
Run-time resource management in fault-tolerant network on reconfigurable chips.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes.
Proceedings of the IEEE International Conference on Control Applications, 2009

2008
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers, 2008

Fault tolerant bit parallel finite field multipliers using LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

Fault-tolerant dynamically reconfigurable NoC-based SoC.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Low test application time resource binding for behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst., 2007

Low overhead DFT using CDFG by modifying controller.
IET Comput. Digit. Tech., 2007

A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

An Analytical Model for Reliability Evaluation of NoC Architectures.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Reliable network-on-chip based on generalized de Bruijn graph.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Using the inter- and intra-switch regularity in NoC switch testing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Single Event Upset Detection and Correction.
Proceedings of the 10th International Conference on Information Technology, 2007

2006
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electron., 2006

Single-Event Upset Analysis and Protection in High Speed Circuits.
Proceedings of the 11th European Test Symposium, 2006

A concurrent testing method for NoC switches.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
A Flow Graph Technique for DFT Controller Modification.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
Proceedings of the 2005 Design, 2005

TED+: a data structure for microprocessor verification.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003


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