Mohammad Hosseinabady
Orcid: 0000-0003-3989-4999
According to our database1,
Mohammad Hosseinabady
authored at least 49 papers
between 2003 and 2021.
Collaborative distances:
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Bibliography
2021
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks.
Array, 2021
2020
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
CoRR, 2020
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.
Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020
Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020
2019
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019
J. Supercomput., 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR, 2018
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the Parallel Computing is Everywhere, 2017
Proceedings of the Parallel Computing is Everywhere, 2017
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2016
IEEE Trans. Computers, 2016
2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2012
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation.
IET Comput. Digit. Tech., 2012
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.
IET Comput. Digit. Tech., 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
2011
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the International Symposium on Electronic System Design, 2011
2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
SystemC Architectural Transaction Level Modelling for Large NoCs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes.
Proceedings of the IEEE International Conference on Control Applications, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 10th International Conference on Information Technology, 2007
2006
J. Low Power Electron., 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2003
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003