Atsushi Hachisuka

According to our database, Atsushi Hachisuka authored at least 5 papers between 1991 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture.

Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.

Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2005

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.

Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

2003

A Low Power Embedded DRAM Macro for Battery-Operated LSIs.

Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

1991

A 45-ns 64-Mb DRAM with a merged match-line test architecture.

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

IEEE J. Solid State Circuits, November, 1991