Daniel L. Stasiak

According to our database, Daniel L. Stasiak authored at least 6 papers between 1999 and 2006.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2006

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.

Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa

IEEE J. Solid State Circuits, 2006

A cycle accurate power estimation tool.

Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Cell Processor Low-Power Design Methodology.

Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang

IEEE Micro, 2005

2001

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology.

Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino

IEEE J. Solid State Circuits, 2001

2000

Custom circuit design as a driver of microprocessor performance.

David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel

IBM J. Res. Dev., 2000

1999

SOI Implementation of a 64-Bit Adder.

J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak

Proceedings of the IEEE International Conference On Computer Design, 1999