Carl J. Anderson

According to our database1, Carl J. Anderson authored at least 8 papers between 1995 and 2009.

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Bibliography

2009
One look into the future of CMOS chip design.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Beyond innovation: dealing with the risks and complexity of processor design in 22nm.
Proceedings of the 46th Design Automation Conference, 2009

2002
The circuit and physical design of the POWER4 microprocessor.
IBM J. Res. Dev., 2002

1998
SOI for digital CMOS VLSI: design considerations and advances.
Proc. IEEE, 1998

1997
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders.
IEEE J. Solid State Circuits, 1997

Floating-body effects in partially depleted SOI CMOS circuits.
IEEE J. Solid State Circuits, 1997

1996
Floating body effects in partially-depleted SOI CMOS circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM J. Res. Dev., 1995


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