Min Zhu
Orcid: 0000-0002-9854-7455Affiliations:
- Micro Innovation Integrated Circuit Design, Wuxi, China
- Tsinghua University, Institute of Microelectronics, Beijing, China (PhD 2012)
According to our database1,
Min Zhu
authored at least 47 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems.
IEEE J. Solid State Circuits, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Compact GF(2) systemizer and optimized constant-time hardware sorters for Key Generation in Classic McEliece.
IACR Cryptol. ePrint Arch., 2022
An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance.
Sci. China Inf. Sci., 2022
Stabilization of two coupled wave equations with joint anti-damping and non-collocated control.
Autom., 2022
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Static boundary feedback stabilization of an anti-stable wave equation with both collocated and non-collocated measurements.
Syst. Control. Lett., 2021
Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers.
Sci. China Inf. Sci., 2021
2020
A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Autom. Control., 2020
IEICE Trans. Inf. Syst., 2020
FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance.
IEICE Electron. Express, 2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the ICCSP 2020: 4th International Conference on Cryptography, 2020
2018
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks.
IEEE Trans. Inf. Forensics Secur., 2017
2016
Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture.
IEEE Trans. Inf. Forensics Secur., 2016
An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform.
IEICE Trans. Inf. Syst., 2016
2015
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding".
IEEE Trans. Multim., 2015
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding.
IEEE Trans. Multim., 2015
A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2014
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture.
Sci. China Inf. Sci., 2014
2013
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip.
IEICE Trans. Inf. Syst., 2013
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.
Sci. China Inf. Sci., 2013
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEICE Trans. Inf. Syst., 2012
Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture.
IEICE Trans. Inf. Syst., 2012
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010
IEICE Trans. Inf. Syst., 2010
Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System.
IEICE Trans. Inf. Syst., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010