Boyu Hu

Orcid: 0000-0003-1132-7677

Affiliations:
  • University of California, Los Angeles, CA, USA


According to our database1, Boyu Hu authored at least 15 papers between 2016 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2025
DRWKV: Focusing on Object Edges for Low-Light Image Enhancement.
CoRR, July, 2025

MGDFIS: Multi-scale Global-detail Feature Integration Strategy for Small Object Detection.
CoRR, June, 2025

Simplify-YOLOv5m: A Simplified High-Speed Insulator Detection Algorithm for UAV Images.
IEEE Trans. Instrum. Meas., 2025


2022
Tree species identification method based on improved YOLOv7.
Proceedings of the 8th IEEE International Conference on Cloud Computing and Intelligent Systems, 2022

2020
A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications.
IEEE J. Solid State Circuits, 2019

2018
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Capacitor-DAC-Based Technique For Pre-Emphasis-Enabled Multilevel Transmitters.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection.
IEEE J. Solid State Circuits, 2017

DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers.
IEEE J. Solid State Circuits, 2017

2016
An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016


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