Jeffrey B. Goeders

According to our database, Jeffrey B. Goeders authored at least 34 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison.

Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders

Proceedings of the International Conference on Field Programmable Technology, 2023

Improving the Reliability of FPGA CRO PUFs.

Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022

Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits.

Hayden Cook, Jacob Arscott, Brent George, Tanner Gaskin, Jeffrey Goeders, Brad L. Hutchings

ACM Trans. Reconfigurable Technol. Syst., 2022

Approaches for FPGA Design Assurance.

Eli Cahill, Brad L. Hutchings, Jeffrey Goeders

ACM Trans. Reconfigurable Technol. Syst., 2022

Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering.

Reilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders

Proceedings of the International Conference on Field-Programmable Technology, 2022

Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF.

Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems.

Benjamin James, Jeffrey Goeders

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays.

Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton

ACM Trans. Reconfigurable Technol. Syst., 2020

Using Novel Configuration Techniques for Accelerated FPGA Aging.

Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis.

Wesley Stirk, Jeffrey Goeders

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

An Overlay for Rapid FPGA Debug of Machine Learning Applications.

Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton

Proceedings of the International Conference on Field-Programmable Technology, 2019

Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs.

Matthew B. Ashcraft, Jeffrey Goeders

Proceedings of the International Conference on Field-Programmable Technology, 2019

On-chip FPGA Debug Instrumentation for Machine Learning Applications.

Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs.

Adam Hastings, Sean Jensen, Jeffrey Goeders, Brad L. Hutchings

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs.

Matthew B. Ashcraft, Jeffrey Goeders

Proceedings of the International Conference on Field-Programmable Technology, 2018

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug.

Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Architecture Exploration for HLS-Oriented FPGA Debug Overlays.

Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ.

Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits.

Jeffrey Goeders, Steven J. E. Wilton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques.

Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices.

Jeffrey Goeders

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

Quantifying observability for in-system debug of high-level synthesis circuits.

Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Systems-on-Chip on FPGAs.

Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton

Proceedings of the FPGAs for Software Programmers, 2016

LegUp High-Level Synthesis.

Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the FPGAs for Software Programmers, 2016

2015

Allowing Software Developers to Debug HLS Hardware.

Jeffrey B. Goeders, Steven J. E. Wilton

CoRR, 2015

Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs.

Jeffrey Goeders, Steven J. E. Wilton

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs.

Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

VTR 7.0: Next Generation Architecture and CAD System for FPGAs.

Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz

ACM Trans. Reconfigurable Technol. Syst., 2014

Power Aware Architecture Exploration for Field Programmable Gate Arrays.

Jeffrey B. Goeders, Steven J. E. Wilton

J. Low Power Electron., 2014

Effective FPGA debug for high-level synthesis generated circuits.

Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry.

Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2012

VersaPower: Power estimation for diverse FPGA architectures.

Jeffrey B. Goeders, Steven J. E. Wilton

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

The VTR project: architecture and CAD for FPGAs from verilog to routing.

Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition.

Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011