Bruna Cardoso Paz

According to our database, Bruna Cardoso Paz authored at least 7 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Transport characterization of CMOS-based devices fabricated with isotopically-enriched ²⁸Si for spin qubit applications.

G. Elbaz, Mikaël Cassé, V. Labracherie, G. Roussely, Benoit Bertrand, Heimanu Niebojewski, Maud Vinet, F. Balestro, Matias Urdampilleta, Tristan Meunier, Bruna Cardoso Paz

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Specificities of linear Si QD arrays integration and characterization.

Heimanu Niebojewski, Benoit Bertrand, E. Nowak, Thomas Bedecarrats, Bruna Cardoso Paz, Lauriane Contamin, Pierre-André Mortemousque, V. Labracherie, L. Brevard, H. Sahin, Jean Charbonnier, C. Thomas, Myriam Assous, Mikaël Cassé, Matias Urdampilleta, Yann-Michel Niquet, François Perruchot, Fred Gaillard, Silvano De Franceschi, Tristan Meunier, Maud Vinet

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology.

Bruna Cardoso Paz, Victor El-Homsy, David J. Niegemann, Bernhard Klemt, Emmanuel Chanrion, Vivien Thiney, Baptiste Jadot, Pierre-André Mortemousque, Benoit Bertrand, Thomas Bedecarrats, Heimanu Niebojewski, François Perruchot, Silvano De Franceschi, Maud Vinet, Matias Urdampilleta, Tristan Meunier

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2017

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K.

Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello

Microelectron. Reliab., 2017

2016

Drain current model for short-channel triple gate junctionless nanowire transistors.

Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello

Microelectron. Reliab., 2016

Analog performance of strained SOI nanowires down to 10K.

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2013

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs.

Michelly de Souza, Bruna Cardoso Paz, Denis Flandre, Marcelo Antonio Pavanello

Microelectron. Reliab., 2013